ad5932 Analog Devices, Inc., ad5932 Datasheet - Page 17

• Manufacturer Part Number: ad5932
• Description: Programmable Frequency Scan Waveform Generator
• Manufacturer: Analog Devices, Inc.

SETTING UP THE FREQUENCY SCAN
As stated in the Frequency Profile section, the AD5932 requires
certain registers to be programmed to enable a frequency scan.
The Setting Up the Frequency Scan section discusses these
registers in more detail.
Start Frequency (F
To start a frequency scan, the user needs to tell the AD5932
what frequency to start scanning from. This frequency is stored
in a 24-bit register called F
entire contents of the F
must be performed: one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, Control Bit B24
(D11) should be set to 1, with the LSBs programmed first.
In some applications, the user does not need to alter all 24 bits
of the F
24-bit register operates as two 12-bit registers, one containing
the 12 MSBs and the other containing the 12 LSBs. This means
that the 12 MSBs of the F
of the 12 LSBs and vice versa. The addresses of both the LSBs
and the MSBs of this register are shown in the following bit map.
D15
1
1
Frequency Increments (Δf)
The value in the Δf register sets the increment frequency for the
scan and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency scan.
At the start of a scan, the frequency contained in the F
register is output. Next, the frequency (F
This is followed by (F
the Δf value by the number of increments (N
to the start frequency (F
scan. Mathematically, this final frequency/stop frequency is
represented by
The Δf register is a 23-bit register that requires two 16-bit writes
to be programmed. Table 7 gives the addresses associated with
both the MSB and LSB registers of the Δf word.
Table 7. Δf Register Bits
D15
0
0
0
F
START
D14
0
0
0
START
D14
1
1
+ (N
register. By setting Control Bit B24 (D11) to 0, the
D13
1
1
1
INCR
D13
0
0
× Δf)
START
START
D12
0
1
1
START
START
)
START
+ Δf + Δf), and so on. Multiplying
START
D12
0
1
register, two consecutive writes
) give the final frequency in the
D11
0
1
word can be altered independently
. If the user wishes to alter the
12 LSBs of Δf
<11…0>
D11 to D0
12 LSBs of F
12 MSBs of F
D10 to D0
11 MSBs of Δf
<22…12>
11 MSBs of Δf
<22…12>
START
INCR
+ Δf ) is output.
START
START
) and adding it
<11…0>
Scan
Direction
N/A
Positive Δf
(F
Negative Δf
(F
<23…12>
START
START
START
+ Δf )
− Δf )
Rev. 0 | Page 17 of 28
Number of Increments (N
An end frequency is not required on the AD5932. Instead, this
end frequency is calculated by multiplying the frequency
increment value (Δf) by the number of frequency steps (N
and adding it to/subtracting it from the start frequency (F
that is, F
with the address shown in the following bit map.
D15
0
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (two increments) and 111111111111
representing the maximum number of increments (4095).
Table 8. N
D11
0000
0000
0000
…
1111
1111
Increment Interval (t
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency scan. The
AD5932 offers the user two choices:
•
•
The desired choice is selected by Bit D13 in the t
shown in the following bit map.
D15
0
0
Programming of this register is in binary form, with the
minimum number being decimal 2. Note that 11 bits, D10 to
D0, of the register are available to program the time interval. As
an example, if MCLK = 50 MHz, then each clock period/base
interval is (1/50 MHz) = 20 ns. If each frequency must be output
for 100 ns, then <00000000101> or decimal 5 must be pro-
grammed to this register. Note that the AD5930 can output each
frequency for a maximum duration of 211 − 1 (or 2047) times
the increment interval.
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
D14
1
1
D14
0
0000
0000
0000
…
1111
1111
START
…
INCR
+ N
D13
0
1
Data Bits
D0
0010
0011
0100
…
1110
1111
D13
0
INCR
× Δ f. The N
D12
x
x
Number of Increments
Two frequency increments. This is the
minimum number of frequency
increments.
Three frequency increments.
Four frequency increments.
…
4094 frequency increments.
4095 frequency increments.
INT
D12
1
)
INCR
D11
x
x
D11
12 bits of N
)
INCR
D10 to D0
11 bits <10…0>
Fixed number of output
waveform cycles.
11 bits <10…0>
Fixed number of clock
periods.
register is a 12-bit register,
INCR
INT
D0
<11…0>
register as
AD5932
START
INCR
)
);