adn8830 Analog Devices, Inc., adn8830 Datasheet - Page 15

• Manufacturer Part Number: adn8830
• Description: Thermoelectric Cooler Controller
• Manufacturer: Analog Devices, Inc.

In this circuit, R
resistance of the inductor combined with the equivalent r
of Q1 and Q2, and R1 is the ESR of C1. The voltage, V
pulse-width modulated waveform that switches between PVDD
and ground. This is a second-order low-pass filter with an exact
cutoff frequency of
Practically speaking, R1 and R2 are several tens of milliohms and
are much smaller than the TEC resistance, which can be a few
ohms. The cutoff frequency can be roughly approximated as
This cutoff frequency should be much lower than the clock
frequency to achieve adequate filtering of the switched output
waveform. Also of importance is the damping factor, , of the
L-C filter. Too low a damping factor will result in a longer
settling time and could potentially cause stability problems for
the temperature control loop. Neglecting R1 and R2 again, the
damping factor is simply
Using the recommended values of L1 = 4.7 µH and C1 = 22 µF
results in a cutoff frequency of 15.7 kHz. With a TEC resistance
of 2 Ω, the damping factor is 0.12. The cutoff frequency can be
decreased to lower the output voltage ripple with slower clock
frequencies by increasing L1 or C1. Increasing C1 may appear
to be a simpler approach as it would not increase the physical
size of the inductor, but there is a potential stability danger in
lowering the damping factor too far. It is recommended that ζ
remain greater than 0.05 to provide a reasonable settling time
for the TEC. Increasing ζ also makes finding the proper PID
compensation easier as there is less ringing in the L-C output
filter. To allow adequate phase and gain margin for the PWM
amplifier, Table III should be used to find the lower limit of
cutoff frequency for a given damping factor.
REV. C
Figure 14. Equivalent Circuit for PWM Amplifier and Filter
ζ =
f
f
C
C
=
=
2
P1
N1
2
2
R
1
1
1
π
π
L
Table III. Minimum L-C Filter Cutoff
0.05
0.1
0.2
0.3
0.5
> 0.707
(
C L
C
V
L
Frequency vs. Damping Factor
L
R
PVDD
X
1 1
1
1
1
1
is the TEC resistance, R2 is the parasitic
R
Q1
Q2
+
2
R
+
L
R2
)
R
C L
L
1 1
L1
R1
C1
f
8
4
2
1.9
1.6
1.5
C, MIN
R
(kHz)
L
OUT A
OUT B
DENOTES
PGND
X
DS, ON
, is the
(25)
(26)
(27)
–15–
Calculating PWM Output Ripple Voltage
Although it may seem that f
output ripple, the ripple voltage is also dependent on the ESR of
C1, shown as R1 in Figure 14. This resistance creates a zero
that turns the second-order filter into a first-order filter at high
frequencies. The location of this zero is
With a clock frequency greater than Z1, and presumably greater
than f
The worst-case voltage ripple occurs when the duty cycle of the
PWM output is exactly 50%, or when OUT A = 0.5
shown in Equation 31
Here it can be directly seen that increasing the inductor value or
clock frequency will reduce the ripple. Choosing a low ESR
capacitor will ensure R1 remains low. Operating from a lower
supply voltage will also help reduce the output ripple voltage
from the L-C filter. With a clock frequency equal to Z1 but
presumably greater than f
Which, if f
A typical 100 µF surface-mount electrolytic capacitor can have
an ESR of over 100 mΩ, pulling this zero to below 16 kHz, and
resulting in an excess of ripple voltage across the TEC. Low ESR
capacitors, such as ceramic or polymer aluminum capacitors,
are recommended instead. Polymer aluminum capacitors can
provide more bulk capacitance per unit area over ceramic ones,
saving board space. Table IV shows a limited list of capacitors
with their equivalent series resistances.
This is by no means a complete list of all capacitor manufacturers
or capacitor types that can be used in the application. The 22 µF
capacitor recommended has a maximum ESR of 35 mΩ, which
puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended
inductor and capacitor listed with a 1 MHz clock frequency will
yield a worst-case ripple voltage at OUT A of about 6 mV.
External FET Requirements
External FETs are required for both the PWM and linear amplifiers
that drive OUT A and OUT B from the ADN8830. Although it
is important to select FETs that can supply the maximum current
required to the TEC, they should also have a low enough resis-
tance (r
efficiency. Other key requirements from these FET pairs are
slightly different for the PWM and linear outputs.
∆OUT A
Z
∆
∆OUT A
∆OUT A
C
OUT A
OUT A
1
, the output voltage ripple is
DS, ON
=
MAX
2
CLK
π
) to prevent excessive power dissipation and improve
R C
1
< Z1, can be further simplified to
MAX
MAX
1 1
=
=
=
V
∆
V
DD
I
≈
=
L
DD
(
× 1
4
32 1 1
16 1 1
V R
D
L f
R
f
DD
CLK
C
L C f
1
R C
(
, the worst-case output voltage ripple is
32 1 1
1
V
C
CLK
–
2
L
DD
can be arbitrarily lowered to reduce
1
L C f
D R
1
CLK
)
2
for f
f
CLK
1
2
(
CLK
for f
CLK
for f
2
+
(
(
1
>
)
CLK
CLK
Z
for f
1
ADN8830
)
<
(
>
Z
CLK
Z
1
1
)
)
=
Z
V
1
DD
)
. As
(28)
(29)
(30)
(31)
(32)
(33)