ir3500a International Rectifier Corp., ir3500a Datasheet
ir3500a
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ir3500a Summary of contents
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... DESCRIPTION The IR3500A Control IC combined with an xPHASE3 to implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a multiphase converter. The XPhase3 expensive, and easier to design while providing higher efficiency than conventional approaches. ...
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... ORDERING INFORMATION Device IR3500A MTRPBF * IR3500A MPBF *Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. ...
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... Relative to VIDSEL Threshold between VR11 with/out Boot Voltage I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT 50.0 K OSC R = 24.5 K OSC R = 7.75 K OSC I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT Compare to V(VCCL) IR3500A ≤ 50.0 K OSC = 0.1µF +/-10%. SS/DEL MIN TYP MAX UNIT -0.5 0 ...
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... Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current R DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current Minimum Voltage Maximum Voltage Measure V(VCCL) – V(EAOUT) Page TEST CONDITION To reach 1.1V = 24.5 K OSC IR3500A MIN TYP MAX UNIT 1.0 2.9 3.5 ms 0.8 2.2 3.25 ms 0.3 1.2 3.0 ms 0.5 1.2 2.3 ...
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... Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure V(VCCL)- V(ROSC/OVP) Page TEST CONDITION = 24.5 K OSC IR3500A MIN TYP MAX UNIT 125 300 600 mV 8 Pulses 825 850 ...
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... V(IIN) ≤ 3.3V 0.5V ≤ V(IIN) ≤ 3.3V Note 1 Note 1 I(PGOOD) = 4mA V(PGOOD) = 5.5V Reference to VDAC Reference to VDAC I(PG)=4mA, V(PG)<300mV, V(VCCL)=0 V(VO) < [V(VOSEN+) – V(LGND Compare to V(VCCL) V(VO) = 100mV I(VRHOT) = 30mA V(VRHOT) = 5.5V Compare to V(VCCL) Compare to V(VCCL) Compare to V(VCCL) IR3500A MIN TYP MAX UNIT - 0.2 0.4 0 MHz 4 ...
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... ROSC BUFFER AMPLIFIER 0. REMOTE SENSE AMPLIFIER + - ERROR AMPLIFIER + - IOCSET IVSETPT IROSC IROSC ROSC BUFFER AMPLIFIER 0. REMOTE SENSE AMPLIFIER + - IR3500A EAOUT 1k FB VSETPT RVDAC VDAC OCSET ROCSET CVDAC LGND ROSC ROSC VO EAOUT SYSTEM SET POINT VOSEN+ VOLTAGE VOSNS- VOSEN- EAOUT 1k FB VSETPT RVSETPT ...
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... VCCL Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. 29 VCCLFB Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. Page PIN DESCRIPTION July 3, 2008 IR3500A ...
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... PWM COMPARATOR - EAIN + ENABLE + VID6 - RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER + ISHARE VID6 - VID6 - 3K + DACIN Figure 4 - PWM Block Diagram IR3500A VCC VCCH RESET GATEH DOMINANT CBST CLK Q VCCL PWM LATCH GATEL BODY PGND BRAKING COMPARATOR CURRENT SENSE ...
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... The inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 6 depicts PWM operating waveforms under various conditions Page Figure 5 - Four Phase Oscillator Waveforms IR3500A July 3, 2008 ...
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... DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) Figure 6 - PWM Operating Waveforms − MAX MIN T = SLEW V O − MAX MIN = T SLEW + BODYDIODE IR3500A DUTY CYCLE DECREASE DUE TO LOAD STEADY-STATE DECREASE (BODY BRAKING) OR FAULT OPERATION (VCC UV, OCP, VID FAULT) July 3, 2008 ...
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... Current Sense Amp CSOUT resistor connected to the ISHARE pin. The ISHARE pins of all the phases are IR3500A + the two time constants match, the July 3, 2008 ...
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... VIDs of less than 0.5V are not supported. The IR3500A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier ...
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... VDAC BUFFER AMPLIFIER OPEN SENSE + LINE DETECT IROSC ISOURCE COMPARATORS + CURRENT ISINK - SOURCE GENERATOR - - + 200mV OPEN SENSE LINE Figure 8 - Block Diagram IR3500A VCCLDRV 400K SS CLEARED POWER NOT OK 1 FAULT LATCH1 FAULT LATCH1 2 FAULT LATCH2 FAULT SET DOMINANT SS RESET ...
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... IR3500A Ignore VID Fault VID Fault Latch YES YES NO NO VID3 VID2 VID1 VID0 Vout( 0.7625 0.7500 ...
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... IR3500A Dec (VID7:VID0) Voltage 01000000 1.21250 01000001 1.20625 01000010 1.20000 01000011 1.19375 01000100 1.18750 01000101 1.18125 01000110 1.17500 01000111 1.16875 01001000 1.16250 01001001 1.15625 01001010 1.15000 01001011 1.14375 01001100 1 ...
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... EA 0.54375 EB 0.53750 EC 0.53125 ED 0.52500 EE 0.51875 EF 0.51250 F0 0.50625 F1 0.50000 F2 n/a F3 n/a F4 n/a F5 n/a F6 n/a F7 n/a F8 n/a F9 n/a FA n/a FB n/a FC n/a FD n/a FE n/a FF IR3500A Dec (VID7:VID0) Voltage 11000000 n/a 11000001 n/a 11000010 n/a 11000011 n/a 11000100 n/a 11000101 n/a 11000110 n/a 11000111 n/a 11001000 n/a 11001001 n/a 11001010 n/a 11001011 n/a 11001100 n/a 11001101 n/a 11001110 n/a 11001111 n/a 11010000 n/a 11010001 n/a 11010010 n/a 11010011 n/a 11010100 ...
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... IR3500A Voltage (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 ...
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... Start-up Sequence The IR3500A has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down slope of the voltage at the SS/DEL pin respectively ...
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... SS/DEL, pull down EAOUT voltage and drive PGOOD low. However, the latches can only be reset by cycling VCCL power. Page VID SOFT START VID SAMPLE VRRDY DELAY TIME (TD2) TIME (TD3) TIME (TD4+TD5) TD4 TD5 IR3500A NORMAL OPERATION July 3, 2008 ...
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... If an over-current condition is again encountered during the soft start cycle, the over- current action will repeat and the converter will be in hiccup mode. Page SOFT START VRRDY DELAY TIME (TD3) TIME (TD2) IR3500A NORMAL OPERATION July 3, 2008 ...
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... Figure 13 - Over Current Protection waveforms during and after soft start Linear Regulator Output (VCCL) The IR3500A has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the resistor divider at VCCLFB pin ...
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... The over-voltage protection comparator monitors Vo pin voltage pin voltage exceeds VDAC by 130mV, as shown in Figure 14, IR3500A raises ROSC/OVP pin voltage to V(VCCL) - 1V, which sends over voltage signal to system. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit, which pulls the converter input low in over voltage conditions ...
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... IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain on until ISHARE pin voltage drops below V(VCCL) - 800mV, which signals the end of over voltage condition. An over voltage fault condition is latched in the IR3500A and can only be cleared by cycling power to the IR3500A VCCL. ...
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... VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ROSC/OVP 1.6V Figure 16 - Over-voltage protection during power-up 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 17 - Over-voltage protection with pre-charging converter output Vo > 1.73V Page 12V IR3500A July 3, 2008 ...
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... If either remote sense line VOSEN+ or VOSEN- or both are open, the output of remote sense amplifier (VO) drops. The IR3500A monitors VO pin voltage continuously voltage is lower than 200 mV, two separate pulse currents are applied to VOSEN+ and VOSEN- pins respectively to check if the sense lines are open. If VOSEN+ is open, a voltage higher than 90% of V(VCCL) will be present at VOSEN+ pin and the output of open line detect comparator will be high ...
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... PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault is registered. Phase Number Determination After a daisy chain pulse is started, the IR3500A checks the timing of the input pulse at PHSIN pin to determine the phase number. This information is used to have symmetrical phase delay between phase switching without the need of any external component. ...
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... VID1 IIN 8 17 VID0 RDRP1 VID0 VDRP RDRP ENABLE VRHOT RFB RCP RHOTSET2 RFB1 CFB RFB2 RHOTSET1 Figure 20 - IR3500A / IR3505 Three Phase AMD Opteron Converter Page FUSE ROVP1 Q3 SCR Q2 U10 ROVP2 1 ISHARE IR3505 2 DACIN PHASE 3 LGND IC 4 PHSIN CVDAC ...
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... VID0 8 17 CDRP RDRP1 VID0 VDRP RDRP ENABLE VRHOT RFB RCP CCP RHOTSET2 RFB1 CFB CCP1 RFB2 RHOTSET1 Figure 21 - IR3500A / IR3505 Six Phase VRM11.0 / VRD11.0 / EVRD11.0 Converter Page FUSE CVCC1 Q3 SCR U10 ROVP2 1 12 ISHARE SW IR3505 2 11 DACIN GATEH PHASE 3 ...
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... C / DEL SS / DEL − CHG after which the error amplifier output is released to allow , − CHG = IR3500A according to the OSC (1) The VID sample . (2) ( (4) − ( − (6) − (7) July 3, 2008 VR . ...
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... LIMIT sw =Ratio of the peak to average current for the inductor Determined by the ROSC and given by Figure 24, OCSET IR3500A ( fixed and can be quantified as OCDEL (10) as defined in VDAC (11) (12) and room temperature L_MAX − (13) ROOM (14) ∗ ...
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... VCCL (min) < VCCLDRV ( max) is the minimum and maximum anticipated input voltage. If the I HOTSET1 is calculated from (22). MAX IR3500A which is the O_NLOFST, is determined by (17), where VSETPT (17) (18) (19) (20) (21) or Darlington configuration can min and R HOTSET2 , the NTC THERM ...
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... MAX CS ∗ CCP1 RFB VO+ CCP RFB1 CFB - RDRP VDRP EAOUT EAOUT CDRP + (b) Type III compensation CP IR3500A )] (22 (23) is the required output impedance of O (25) and C removed. DRP DRP CCP1 RCP CCP FB - EAOUT EAOUT VDAC + and C from (26) and (27), where L CP July 3, 2008 ...
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... ∗ and C from (33) and (34 ∗ ∗ ∗ are not needed. Choose the crossover frequency fc between 1/10 and 1 IR3500A (26) (27) (28) (29) according to (30), and determine C (30) (31) (32) (33) (34) (35) July 3, 2008 and FB ...
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... Switching Frequency: f =250 kHz SW Output Inductors: L=470 nH Output Capacitors: Polymer, C=560uF, R IR3500A EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, R frequency of 250kHz per phase, choose R 11.9 uA. Soft Start Capacitor C SS/DEL Determine the soft start capacitor from the required soft start time. ...
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... TOFST CS OCSET − 3 − ∗ IR3500A − 6 ∗ ( 100 − Ω 11.9uA with OCSET . CS ⋅ ( − 108 ) 082 ⋅ − 108 ...
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... EXP [ 3520 T MAX _ ROOM − VCCL . − ( 142 931 * ) and C . DRP CP CP IR3500A DRP =20k , and calculate R VCCLFB2. (19) (20) (21) and R HOTSET2 =3520, and the NTC thermistor THERM 1 1 − = Ω 142 + + 273 115 273 Ω ...
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... SW Output Inductors: L=100 nH Output Capacitors: Ceramic, C=22uF, R IR3500A EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, R switching frequency of 800kHz per phase, choose R Soft Start Capacitor C SS/DEL Determine the soft start capacitor to meet the specifications of the delay time. ...
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... Resistor R VDAC VDAC 18 nF − Ω − − 3 − = ∗ 3850 * L _ MAX ROOM IR3500A mS − 6 ∗ − = Ω 100 40uA with OCSET . CS July 3, 2008 ...
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... < Ω 660 HOTSET1 is, MAX 1 3 − EXP [ 3520 ( * T 273 _ ROOM IR3500A ⋅ − 108 ) 126 ⋅ − 108 ) DRP =20k , and calculate R VCCLFB2. mA (19) (20) (21) and R HOTSET2 =3520, and the NTC thermistor ...
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... ∗ IR3500A , choose R =3.65k . Ω HOTSET1 =6.65k . DRP = 165 kHz − =2.2nF. DRP − ∗ ∗ Ω ...
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... Figure 23 - Frequency variation with ROSC. Figure 24 - ISETPT, OCSET with ROSC. Page IR3500A July 3, 2008 ...
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... VCCL VCCL VOSNS+ VOSNS+ VOSNS- VOSNS- HOTSET HOTSET VRRDY VRRDY VRHOT VRHOT VIDSEL VIDSEL ENABLE ENABLE To SYSTEM To SYSTEM IR3500A . Avoid using any via for the connection Phase Phase ICs ICs Thermistor Thermistor To Voltage To Voltage Remote Remote Sense Sense To VCCL To VCCL ...
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... Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. Page IR3500A July 3, 2008 ...
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... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented or plugged from bottom boardside with solder resist. Page IR3500A July 3, 2008 ...
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... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page IR3500A July 3, 2008 ...
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... C/W, θ JA Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information. www.irf.com IR3500A C/W JC TAC Fax: (310) 252-7903 ...