ir3082pbf International Rectifier Corp., ir3082pbf Datasheet - Page 14

• Manufacturer Part Number: ir3082pbf
• Description: Xphase Amd Opterontm/athlon 64tm Control Ic
• Manufacturer: International Rectifier Corp.

IR3082PbF
Remote Voltage Sensing
To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects
directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a
separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed
transients are fed directly into the error amp without delay.
Soft Start, Over-Current Fault Delay, and Hiccup Mode
The IR3082PbF has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay
and hiccup mode timing. A charge current of 66uA and discharge current of 6uA control the up slope and down
slope of the voltage at the SS/DEL pin respectively. Soft start-up waveforms are shown in Figure 10.
Figure 11 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL
pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error
amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset until it
reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.83V
and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.9V, indicating the end of the soft start.
Under Voltage Lock Out and VID=11111 faults as well as a low signal on the ENABLE input immediately sets the
fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If
the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since
over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-
current fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set
the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge
below the 115mV offset of the delay comparator, the Fault latch will be set pulling the error amp’s output low
inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The delay can be reduced by adding a
resistor in series with the delay capacitor. The delay comparator’s offset voltage is reduced by the drop in the
resistor caused by the discharge current. To prevent the charge current from creating an offset exceeding the
SS/DEL to FB input offset voltage the value of the resistor should be 10KΩ or less to avoid interference with the soft
start function.
The SS/DEL capacitor will continue to discharge until it reaches 0.2V and the fault latch is reset allowing a normal
soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault latch will be
set without any delay and hiccup mode will begin. During hiccup mode the 11 to 1 charge to discharge ratio results
in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs.
If SS/DEL pin is pulled below 0.9V, the converter can be disabled.
Under Voltage Lockout (UVLO)
The UVLO function monitors the IR3082PbF’s VCC supply pin and ensures that IR3082PbF has a high enough
voltage to power the internal circuit. The IR3082PbF’s UVLO is set higher than the minimum operating voltage of
compatible Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset
when VCC exceeds 9.75V and there is no other fault. If the VCC voltage drops below 9.0V the fault latch will be set.
For converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent
operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides
a simple 5V UVLO function.
Page 14 of 33
01/31/05