ltc1415csw-trpbf Linear Technology Corporation, ltc1415csw-trpbf Datasheet - Page 14

• Manufacturer Part Number: ltc1415csw-trpbf
• Description: 12-bit, 1.25msps, 55mw Sampling A/d Converter
• Manufacturer: Linear Technology Corporation

LTC1415
APPLICATIONS
limitations at high input frequencies (THD = 75dB at
600kHz). The ADC in Figure 10e has a full scale of 2.048V
and a common mode of 2.27V. The reduced signal swing
of this circuit results in improved distortion at higher input
frequencies (THD = 82dB at 600kHz) but with worse
SINAD at low frequencies (SINAD = 70dB at 100kHz).
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics
for the LTC1415. The code transitions occur midway
between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output
is straight binary with 1LSB = FS/4096 = 4.096V/4096
= 1mV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the – A
0.5mV (i.e., 0.5LSB) at +A
– A
0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.0945V (FS – 1.5LSBs)
is applied to the analog input and R7 is adjusted until
14
IN
input (R8) until the output code flickers between
111...111
111...110
111...101
000...010
000...001
000...000
Figure 11a. LTC1415 Transfer Characteristics
1LSB
IN
U
input. For zero offset error apply
INPUT VOLTAGE (V)
INFORMATION
U
IN
and adjust the offset at the
W
FS – 1LSB
LTC1415 • F11a
U
the output code flickers between 1111 1111 1110 and
1111 1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1415, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
is critical to prevent digital noise from being coupled to the
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. Particular care should
be taken not to run any digital track alongside an analog
signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the DV
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
ANALOG
INPUT
5V
DD
Figure 11b. Offset and Full-Scale Adjust Circuit
100
bypass capacitor should also be connected to
R1
50k
R8
R2
47k
10 F
47k
R5
50k
24k
R7
R6
24k
R3
0.1 F
100
R4
1
2
3
4
5
+A
–A
V
REFCOMP
AGND
REF
IN
IN
LTC1415
LTC1415 • F11b