st52t430 STMicroelectronics, st52t430 Datasheet
st52t430
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... Low cost Programmer „ Gang Programmer Timer ADC SCI Watchdog PWM 3x8-bit 8-Ch Yes Yes 3x8-bit 8-Ch Yes Yes 3x8-bit 8-Ch Yes Yes 3x8-bit 8-Ch Yes Yes ST52T430/E430 PRELIMINARY DATASHEET Operating I/O Package Supply 3.0-5 Sdip32 Sso34 Tqfp32 3.0-5 Sdip32 Sso34 Tqfp32 3.0-5 Sdip32 Sso34 Tqfp32 3.0-5 Csdip32w 1/88 ...
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TABLE OF CON- TENTS 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST Five Family, which can perform both boolean and fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. ST52x430 is produced by STMicroelectronics using the reliab le hig h performance CMOS process, including integrated-on-chip peripherals that allow maximization of system reliability, decreasing system costs and minimizing the number of external components ...
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EPROM programming. A signal applied to PB1 is used to increment the memory address; the data is supplied to PORT A (see EPROM programming for further details). 1.2.2 Working mode. Below are the control signals ...
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Figure 1.2 SSO34 Pin Configuration RESET OSCOUT OSCIN INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PB0/Ain0 PB1/Ain1 PB2/Ain2 PB3/Ain3 Figure 1.3 PSDIP32 Pin Configuration RESET OSCOUT OSCIN TEST INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 TX/PC4 RX/PC5 PB0/Ain0 PB1/Ain1 PB2/Ain2 PB3/Ain3 ...
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Table 1.1 ST52x430 SSO34 & PSDIP32 Pin list SSO34 SDIP32 NAME Pins Pins 1 1 RESET 2 2 OSCOUT 3 3 OSCIN 4 4 TEST 5 5 INT/PC0 6 6 T0OUT/PC1 7 7 T1OUT/PC2 8 8 T2OUT/PC3 9 9 TX/PC4 ...
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Table 1.2 ST52x430 TQFP32 Pin list TQFP32 NAME Pins 1 INT/PC0 2 T0OUT/PC1 3 T1OUT/PC2 4 T2OUT/PC3 5 TX/PC4 6 RX/PC5 7 PC6 8 PC7 9 Ain0/PB0 10 Ain1/PB1 11 Ain2/PB2 12 Ain3/PB3 13 V DDA 14 GNDA 15 Ain4/PB4 ...
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Pin Description GNDA DDA PP noise disturbances, the power supply of the digital part is kept separate from the power supply of the analog part. V Main Power Supply Voltage ...
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Figure 1.4 ST52X430 Block Diagram PROGRAM MEMORY EPROM CORE INTERRUPTS CONTROLLER ALU & DPU DECISION PROCESSOR CONTROL UNIT Register File 256 bytes PC POWER SUPPLY VDD VPP TIMER/PWM 0 TIMER/PWM 1 TIMER/PWM 2 PORT A PORT C Input registers PORT ...
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INTERNAL ARCHITECTURE ST52x430 is made up of the following blocks and peripherals: Control Unit (CU) and Data Processing Unit (DPU) ALU / Fuzzy Core EPROM 256 Byte RAM Clock Oscillator Analog Multiplexer and A/D Converter 3 PWM / Timers ...
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Figure 2.1 Data Processing Unit (DPU) E PROM INPU T S PER IPH ERAL S ADD STAC K POINT Figure 2.2 CU/DPU Block Diagram ...
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The ST52x430 core uses flags that correspond to the actual mode. As soon as an interrupt is generated the ST52x430 core uses the interrupt flags instead of the normal flags. Each interrupt level has its own set of flags, which ...
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The STACK POINTER indicates the first level available to store data. When a subroutine call or interrupt request occurs, the content of the PC and the current set of flags are stored into the level located by the STACK POINTER. ...
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Table 2.2 Input Registers IR MNEMONIC NAME STACK_POINTER CHAN 0 CHAN 1 CHAN 2 CHAN 3 CHAN 4 CHAN 5 CHAN 6 CHAN 7 PORT_A PORT_B PORT_C PWM_ 0_COUNT PWM_ 0_ STATUS PWM_ 1_ COUNT PWM_ 1_ STATUS PWM_ 2_ ...
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Table 2.3 Configuration Registers (continued) CONFIGURATION REGISTER REG_CONF 4 REG_CONF 5 REG_CONF 6 REG_CONF 7 REG_CONF 8 REG_CONF 9 REG_CONF 10 REG_CONF 11 REG_CONF 12 REG_CONF 13 REG_CONF 14 REG_CONF 15 REG_CONF 16 REG_CONF 17 REG_CONF 18 REG_CONF 19 REG_CONF ...
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Table 2.4 Output Registers OR MNEMONIC NAME PORT_ A PORT_ B PORT_C PWM_0_COUNT PWM_0_RELOAD PWM_1_COUNT PWM_1_RELOAD PWM_ 2_ COUNT PWM_2_RELOAD SCI_TX_DATA 2.4 Arithmetic Logic Unit The 8-bit Arithmetic Logic Unit (ALU) allows the performance of arithmetic calculations and logic instructions, ...
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Table 2.5 Load instructions PGSET PGSET const Table 2.6 Arithmetic & Logic instructions set Mnemonic Instruction ADD ADD regi, regj ADDO ADDO regi, regj AND AND regi, regj ASL ASL regi ASR ASR regi DEC DEC regi DIV DIV regi, ...
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Table 2.8 Interrupt Instructions Set (continued) MDGI RETI RINT RINT INT UDGI UEGI WAITI Table 2.9 Control Instructions Set Mnemonic Instruction FUZZY NOP WDTRFR WDTRFR WDTSLP WDTSLP Notes: I affected - not affected Figure 2.5 Multiplication RAM ...
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... Writing and Verify. 8191 4095 Fuzzy and Boolean Algorithms 2047 MemAdd+1 MemAdd Mbfs Parameters 21 20 INT_EXT INT_SCI INT_TIMER/PWM2 INT_TIMER/PWM1 INT_TIMER/PWM0 INT_ADC 3 2 Program Instruction First Address 0 ST52T430 ST52T430 2047 4095 8191 Program Instruction Set Mbfs Setting and Program Instruction Set Interrupt Vectors 23/88 ...
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Table 3.2 EPROM Control Register OPERATION REGISTER VALUE Stand By Memory Reading/Verify Memory Unlock and Lock Status Reading Memory Writing Memory Lock ID CODE Writing Memory Lock Status Reading/Verify ID CODE Reading/ Verify Figure 3.2 Eprom Programming Timing PA(0:7) RST_ADD ...
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PHASE and RST_ADD signals are active low, RST_CONF signal is active high. Port A is used for the memory data I/O. (See Table 3.2 for pin reference on the different packages) . Memory may be locked by means of the ...
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EPROM Read/Verify Margin Mode. The read phase is executed with V instead of the verify phase that needs V 12V 5%. The Memory Verify operation is available in order to verify the accuracy of the data written. A Memory ...
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INTERRUPTS The Control Unit (CU) responds to peripheral events and external events via its interrupt channels. When such an events occur, if the related interrupt is not masked and according to a priority order, the current program execution can ...
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Routine associated to the interrupt with higher priority will start. In order to avoid possible conflicts between interrupt masking set in the main program, or inside high level language compiler macros, the GIP is hung up through the User Global ...
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Table 4.2 Interrupts Description Name Description INT_ADC ADC INT_PWM/ PWM/TIMER 0 TIMER0 INT_PWM/ PWM/TIMER 1 TIMER1 INT_PWM/ PWM/TIMER 2 TIMER2 INT_SCI SCI External INT_EXT Interrupt (INT) Figure 4.4 Interrupt Configuration Register Priority Int Programmable Int ...
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Figure 4.5 Interrupt Configuration Register 17 & 18 REG_CONF18 D15 D14 D13 D12 D11 D10 4.5 Interrupt Priority Seven priority levels are available: level 6 has the lowest priority, level 0 has the highest priority. Level 6 is associated to ...
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Figure 4.6 Example of a sequence of Interrupt requests PRIORITY LEVEL MAIN PROGRAM REMARK: The Interrupt priority must be set at the beginning of the main program, because at the RESET REG_CONF1=’00000000’, condition ...
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CLOCK, RESET & POWER SAVING MODE 5.1 System Clock The ST52x430 Clock Generator module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals and it is designed to require a minimum number components. The ST52x430 ...
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During WAIT mode, Interrupts are enabled. The MCU will remain in Wait mode until an Interrupt or a RESET occurs, whereupon the Program Counter jumps to the interrupt service routine or RESET occurs, ...
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Figure 5.5 HALT Flow Chart HALT INSTRUCTION SKIPPED NO RESET YES OSCILLATOR PERIPHERALS CLOCK CPU CLOCK 1000000 CPU CLOCK CYCLES DELAY RESET CPU AND RESTART USER PROGRAM 34/88 HALT INSTRUCTION YES WATCHDOG ENABLED NO OSCILLATOR OFF PERIPHERALS CLOCK OFF CPU ...
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I/O PORTS 6.1 Introduction ST52x430 devices feature flexible individually programmable multi-functional input/output lines. Refer to the following figure for specific pin allocations. 23 I/O lines, grouped in 3 different ports are available on the ST52x430: PORT ...
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Figure 6.2 Port B Functional Blocks FROM CONFIGURATION REGISTER TO INPUT REGISTER FROM OUTPUT REGISTERS FROM CONFIGURATION REGISTER Table 6.2 Input Register and I/O Ports PORT A PORT 6.3 Output Mode The output configuration is ...
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Table 6.1) The structure of these registers is illustrated in the following tables. Each bit of the configuration registers determines the I/O mode of the related port pin. Table 6.4 Ports A REG_CONF 4 Bit Name ...
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Table 6.6 Port C REG_CONF 15 Bit Name Value Set the pin INT/PC0 Set the pin INT/PC0 in 1 Set the pin T0OUT/ 0 PC1 in Output Mode 1 D1 Set the pin T0OUT/ 1 PC1 ...
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PWM/Timers Alternate Functions The pins of Port A and C can be configured the three PWM/Timers available on the ST52x430. The configuration of these pins is performed by using the Configuration Registers REG_CONF 12 and ...
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Figure 6.3 Configuration Register 12 REG_CONF 12 DIGITAL PORT Figure 6.4 Configuration Register 16 REG_CONF 16 DIGITAL PORT 40/88 PA1T: Pin PA1/T0OUT setting PA2T: ...
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... Fuzzy Inference The block diagram shown in Figure 7.1 describes the different steps performed during a Fuzzy algorithm. The ST52T430/E430 Core allows for the implementation of a Mamdani type fuzzy inference with crisp consequents. Inputs for fuzzy inference are stored in 8 dedicated Fuzzy input registers. ...
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... By using the previous memorization method different kinds of triangular Membership Functions may be stored. Figure 7.5 shows some examples of valid Mbfs that can be defined in ST52T430/ E430. Each Mbf is then defined storing 3 bytes in the first Kbyte of the Program/Data Memory. ...
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Figure 7.5 Example of valid Mbfs 7.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn’t have a shape, like a traditional Mbf, and is characterized by a ...
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Example 1: IF Input IS NOT Mbf AND Input codified by the following instructions: calculates the NOT LDN 1 1 fixes the value of Input LDP 4 12 FZAND implements the operation AND between the results obtained ...
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A/D CONVERTER 8.1 Introduction The A/D Converter of ST52x430 is an 8-bit analog to digital converter with analog inputs offering 8 bit resolution with a total accuracy of 1 LSB and a typical conversion time of ...
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If input voltage is less than V SS low) then the result is equal to 00h. The A/D converter is linear and the digital result of the conversion is provided by the following formula: 255inputVoltage ----------------------------------------------- - Digitalresult = referenceVoltage ...
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One Channel Continuous Mode In this mode (SEQ = ‘0’’ ‘1’) a continuous conversion flow is entered by a starting event on the channel selected by the CH0, CH1, CH2 bits For example: CH(2:0) = ‘011’ means continuous ...
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WATCHDOG TIMER 9.1 Operational Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which cause the application program to abandon its normal sequence. ...
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Register Description The WDT timeout is defined by setting the value of the REG_CONF 2. The first 4 bits of this register are used, obtaining 16 different delays as illustrated in Table 9.2. In Table 9.2 timeout is expressed ...
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PWM/TIMER ST52x430 offers three on-chip peripherals:TIMER0, TIMER1 and TIMER2. The ST52x430 timers have the same internal structure. The timer consists of an 8-bit counter with a 16-bit programmable prescaler, giving a 24 maximum count of 2 (see Figure 10.1). ...
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Figure 10.2 Timer 0 External START/STOP Mode start Level start Edge Reset Clock Counted 0 Value NOTE: The external clock signal applied on the T0CLK pin must have a frequency at least two times smaller than the internal master clock. ...
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Figure 10.4 PWM Mode with Auto Reload 255 compare value reload register 0 PWM Output EDGE(Period Counter): After reset, on the first T0STRT rising edge, TIMER 0 starts counting and at the next rising edge it stops. In this manner, ...
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The Output Register PWM_x_RELOAD value is automatically reloaded when Counter x restarts counting. The 16-bit Prescaler x divides the master clock, CLKM, or, only for TIMER0, the external T0CLK signal, by the 16-bit Prescaler x. NOTE: The external clock signal, ...
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Table 10.1 Configuration Register 5 Description Bit Name 0 TIRST0 1 TERST 2 TISTR0 3 TESTR 4 INTE0 5 6 INTSL0 7 T0MODE Figure 10.5 Configuration Register 5 REG_CONF 5 TIMER ...
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Table 10.2 Configuration Register 6 Description Bit Name PRESC0 TMRW0 Figure 10.6 Configuration Register 6 REG_CONF 6 TIMER Value 00000 TIMER0 ...
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Table 10.3 Configuration Register 7 Description Bit Name 0 T0RST 1 2 T0STR 3 4 T0CLK 5 T0MSK 6 T2MSK 7 T1MSK Figure 10.7 Configuration Register 7 REG_CONF 7 TIMER 0, TIMER 1, TIMER2 ...
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Table 10.4 Config. Register 8 Description Bit Name 0 TIRST1 TISTR1 INTE1 5 6 INTSL1 7 T1MODE Figure 10.8 Configuration Register 8 REG_CONF 8 TIMER ...
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Table 10.5 Config. Register 9 Description Bit Name PRESC1 TMRW1 Figure 10.9 Configuration Register 9 REG_CONF 9 TIMER 58/88 Value 00000 ...
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Table 10.6 Config. Register 10 Description Bit Name Value 0 TIRST2 TISTR2 INTE2 INTSL2 7 T2MODE Figure 10.10 Configuration Register 10 REG_CONF 10 TIMER ...
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Table 10.7 Config. Register 11 Description Bit Name Value 00000 0 00001 00010 00011 00100 1 00101 00110 00111 2 PRESC2 01000 01001 01010 3 01011 01100 01101 01110 4 01111 10000 5 TMRW2 Figure 10.11 ...
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Table 10.8 Config. Register 12 Description Bit Name Value 0 PA1 1 PA2 2 PA3 3 PASZ Figure 10.12 Configuration Register 12 REG_CONF 12 DIGITAL PORT ...
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Table 10.9 Config. Register 16 Description Bit Name Value 1 0 PC1 PC2 PC3 PC4 0 4 Figure 10.13 Configuration Register ...
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Table 10.10 Input Registers 13. PWM_0_STATUS Bit Name Value 0 STR0 RST0 0 TIMER 0 is RESET Table ...
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SERIAL COMMUNICATION INTERFACE The Serial Communication integrated into the ST52x430 fuzzy processor provides a general purpose peripheral, which links several widely distributed MCU’s through their SCI subsystem. SCI offers a serial interface providing communication with common baud rates up ...
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When the SCI Receiver is in IDLE status waiting for the START condition, which is obtained with a logic level 0, consecutive to a logic level 1. This condition is detected if a logic level 0 is sampled ...
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A frame error can occur if the parity check hasn’t been successfully achieved or if the STOP bit hasn’t been detected. If the Recovery Buffer Block receives 10 consecutive bits at logic level 0, a break error occurs and an ...
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Figure 11.3 SCI Status Input Register SCI_ST Input Register the core supplies new data it can’t be loaded in the SCDR_TX block until the current data hasn’t been unloaded on ...
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ELECTRICAL CHARACTERISTICS 12.1 Parameter Conditions Unless otherwise specified, all voltages are referred to V ss. 12.1.1 Minimum and Maximum values. Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of environment temperature, supply voltage ...
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Table 12.1 Voltage Characteristics Symbol DDA SSA and V Variation between different digital power pins V | DDA SSA Variation between digital and analog ground pins - SSA SSX ...
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Recommended Operating Condition Operating condition: V =5V 10 Table 12.4 Recommended Operating Conditions Symbol Parameter 2) Operating Supply Programming Voltage PP V Output Voltage O V Analog Supply Voltage DDA, V Analog Ground SSA ...
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Supply Current Characteristics Supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the ...
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Table 12.6 Supply Current in HALT Mode Symbol Parameter I Supply current in HALT mode DDA Notes: 1. Typical data is based All I/O pins in input mode with a static value at V ...
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Clock and Timing Characteristics Operating Conditions: V =5V 5%, TA=0/125 C, unless otherwise specified DD Table 12.8 General Timing Parameters Symbol Parameters f Oscillator Frequency osc t Clock High CLH t Clock Low CLL t Setup SET t Hold ...
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Memory Characteristics Subject to general operating conditions for V Table 12.9 RAM and Registers Symbol Parameter Data retention mode Table 12.10 EPROM Program Memory Symbol Parameter W UV lamp ERASE 2) t ERASE Erase time t ...
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ESD Pin Protection Strategy In order to protect an integrated circuit against Electro-Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. Stress generally affects the circuit elements, which are connected to the ...
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Multi-supply Configuration. When several types of ground (V power supply ( ,...) are available for any DD DDA reason (better noise immunity...), the structure Figure 12.10 ESD Protection for Multisupply Configuration VDD (4) VSS BACK TO BACK ...
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Port Pin Characteristics 12.8.1 General Characteristics. Subject to general operating condition for V Symbol Parameter CMOS type low level input voltage. Port B pins. (See Fig 11.13 TTL type Schmitt trigger low level input voltage. Port A ...
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Subject to general operating conditions for V Table 12.11 Output Voltage Levels Symbol Parameter Output low level voltage for standard I pin when 8 pins are sunk at same time. Output high level voltage for standard I/ ...
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Subject to general operating condition for V Table 12.12 Output Driving Current Symbol Parameter R Input protection resistor S C Pin Capacitance S Figure 12.14 Port A and Port C pin Equivalent Circuit Device Input/Output Figure 12.15 Port B Pin ...
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Control Pin Characteristics 12.9.1 RESET pin. Subject to general operating conditions for V Table 12.13 Reset pin Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys t General ...
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A/D Characteristics Subject to general operating conditions for V Symbol Parameter Res Resolution A Total Accuracy TOT t Conversion Time C V Conversion Range AN V Zero Scale Voltage ZI V Full Scale Voltage FS Analog Input Current ...
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Table 12.15 SS034 PACKAGE MECHANICAL DATA DIM MIN A 2.4638 A1 0.127 B 0.3556 C 0.23114 D 17.7292 E 7.4168 e H 10.16 h 0.635 0.6096 82/88 mm TYP. MAX 2.6416 0.097 0.2921 0.005 ...
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Table 12.16 PDIP32 Shrink PACKAGE MECHANICAL DATA DIM MIN eAl TYP. MAX 0.140 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.100 ...
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Table 12.17 CSDIP32W Shrink PACKAGE MECHANICAL DATA DIM MIN 84/88 mm TYP. MAX 0.097 0.025 0.016 0.035 0.008 1.168 1.042 0.382 0.065 0.170 G1 e ...
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Table 12.18 TQFP32 PACKAGE MECHANICAL DATA DIM MIN A A1 0.05 A2 1.35 B 0. TYP. MAX 1.60 0.15 0.002 1.40 1.45 0.053 0.37 0.45 0.012 ...
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... Care must be taken only to use resources available on the target device. Figure 12.16 Device Types Selection Guide ST52 t nnn PART NUMBER ST52T430K1M6 ST52T430K2M6 ST52T430K3M6 ST52T430K1B6 ST52T430K2B6 ST52T430K3B6 ST52T430K1T6 ST52T430K2T6 ST52T430K3T6 ST52E430K3D6 ST52X430/KIT 86/88 TEMPERATURE RANGE - °C PACKAGES PDIP ...
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87/88 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...