ltc2631-z Linear Technology Corporation, ltc2631-z Datasheet - Page 22

• Manufacturer Part Number: ltc2631-z
• Description: Single 12-/10-/8-bit I 2c Vout Dacs With Bidirectional Reference
• Manufacturer: Linear Technology Corporation

LTC2631
OPERATION
in this manner but does not acknowledge a read operation;
in that case, SDA is retained HIGH during the period of
the Acknowledge clock pulse.
Chip Address
The state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-LZ)
determines the slave address of the part. These pins can
each be set to any one of three states: V
This results in 9 (LTC2631-HZ/LTC2631-LZ) or 3 (LTC2631-
HM/LTC2631-LM) selectable addresses for the part. The
slave address assignments are shown in Tables 1 and 2.
Table 1. Slave Address Map (LTC2631-Z)
Table 2. Slave Address Map (LTC2631-M)
In addition to the address selected by the address pins,
the part also responds to a global address. This address
allows a common write to all LTC2631 parts to be accom-
plished using one 3-byte write transaction on the I
The global address, listed at the end of Tables 1 and 2, is
a 7-bit hardwired address not selectable by CA0/CA1. If
another address is required, please consult the factory.
22
GLOBAL ADDRESS
GLOBAL ADDRESS
FLOAT
FLOAT
FLOAT
GND
GND
GND
CA1
V
V
V
CC
CC
CC
FLOAT
GND
CA0
V
CC
FLOAT
FLOAT
FLOAT
GND
GND
GND
CA0
V
V
V
CC
CC
CC
A6
A6
0
0
0
0
0
0
0
0
0
1
0
0
0
1
A5
A5
0
0
0
0
1
1
1
1
1
1
0
0
0
1
A4
A4
1
1
1
1
0
0
0
0
1
1
1
1
1
1
A3
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC
, GND or fl oat.
A2
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
A1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
2
C bus.
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The maximum capacitive load allowed on the CA0/CA1
address pins is 10pF , as these pins are driven during ad-
dress detection to determine if they are fl oating.
Write Word Protocol
The master initiates communication with the LTC2631 with
a START condition and a 7-bit slave address followed by the
Write bit (W) = 0. The LTC2631 acknowledges by pulling
the SDA pin low at the 9th clock if the 7-bit slave address
matches the address of the part (set by CA0/CA1) or the
global address. The master then transmits three bytes
of data. The LTC2631 acknowledges each byte of data
by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2631 executes the command specifi ed in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2631 does not acknowledge the
extra bytes of data (SDA is high during the 9th clock).
The format of the three data bytes is shown in Figure 3.
The fi rst byte of the input word consists of the 4-bit com-
mand, followed by four don’t care bits. The next two bytes
contain the 16-bit data word, which consists of the 12-,
10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8
don’t-care bits (LTC2631-12, LTC2631-10 and LTC2631-8
respectively). A typical LTC2631 write transaction is
shown in Figure 4.
The command bit assignments (C3-C0) are shown in
Table 3. The fi rst four commands in the table consist of
write and update operations. A write operation loads a
16-bit data word from the 32-bit shift register into the
input register. In an update operation, the data word is
copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
2631fa