ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 26

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC2484
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to the LTC2484. For
reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2484 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver output pin will also eliminate this problem without
additional power dissipation. The actual resistor value
depends upon the trace impedance and connection
topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input archi-
tecture reduces the converter’s sensitivity to ground
currents.
Particular attention must be given to the connection of the
F
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such
perturbations can occur due to asymmetric capacitive
coupling between the F
26
O
signal when the LTC2484 is used with an external
U
O
U
signal trace and the converter
W
U
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
nals. When the F
converter, substantial AC current is flowing in the loop
formed by the F
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
the differential input and reference connections. Even
when F
EMI threats which will be minimized by following good
layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2484 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance R
driving an analog input pin (IN
considered to form, together with R
Figure 11), a first order passive network with a time
constant τ = (R
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator, the LTC2484’s front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency f
used, the sampling period is 2.5/f
error of less than 1ppm, τ ≤ 0.178/f
O
is not driven, other nearby signals pose similiar
O
O
S
signal trace and the input/reference sig-
connection trace, the termination and the
O
+ R
signal is parallel terminated near the
SW
O
signal as well as the loop area for
) • C
EQ
+
, IN
. The converter is able to
–
EOSC
, V
EOSC
REF
SW
and, for a settling
+
.
or GND) can be
and C
EQ
EOSC
(see
2484fa
is
S