ltc2428 Linear Technology Corporation, ltc2428 Datasheet - Page 24

• Manufacturer Part Number: ltc2428
• Description: 4-/8-channel 20-bit ?power No Latency Delta-sigma Adc
• Manufacturer: Linear Technology Corporation

APPLICATIONS
LTC2424/LTC2428
A similar situation may occur during the sleep state when
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as t
internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions
where CSADC remains LOW after detecting EOC = 0. This
situation is easily avoided by adding an external 10k pull-
up resistor to the SCK pin.
DIGITAL SIGNAL LEVELS
The LTC2424/LTC2428’s digital interface is easy to use.
Its digital inputs (F
in External SCK mode of operation) accept standard
TTL/CMOS logic levels and can tolerate edge rates as slow
24
SCKCLK
CSMUX
CSADC
SDO
D
IN
TEST EOC
t
EOCtest
DON’T CARE
O
U
Hi-Z
, CSADC, CSMUX, CLK, D
Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram
INFORMATION
U
TEST EOC
Hi-Z
W
BIT23
BIT22
EOCtest
TO 1.12V
IN
–0.12V
U
BIT21
SIG
and SCK
TO V
2.7V TO 5.5V
0.1V
REF
REF
), the
BIT20
CC
EXR
BIT19 BIT18
MSB
V
FS
CH0
TO CH7
MUXOUT
ADCIN
ZS
GND
LTC2424/LTC2428
CC
SET
SET
as 100 s. However, some considerations are required to
take advantage of exceptional accuracy and low supply
current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the accuracy of the LTC2424/LTC2428,
it is very important to minimize the ground path imped-
ance which may appear in series with the input and/or
reference signal and to reduce the current which may flow
through this path. The ZS
nected directly to the signal ground.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.
CSMUX
CSADC
SDO
SCK
CLK
BIT12 BIT11 BIT10 BIT9
D
F
IN
O
EN
D2
V
CC
D1
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
CS
BIT8
D0
SET
10k
pin (Pin 5) should be con-
Hi-Z
DON’T CARE
TEST EOC
24248 F17