ltc3025edc-trpbf Linear Technology Corporation, ltc3025edc-trpbf Datasheet - Page 6

• Manufacturer Part Number: ltc3025edc-trpbf
• Description: 300ma Micropower Vldo Linear Regulator
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
LTC3025
BIAS (Pin 1): BIAS Input Voltage. BIAS provides internal
power for LTC3025 circuitry. The BIAS pin should be lo-
cally bypassed to ground if the LTC3025 is more than a
few inches away from another source of bulk capacitance.
In general, the output impedance of a battery rises with
frequency, so it is usually advisable to include an input
bypass capacitor in battery-powered circuits. A capacitor
in the range of 0.01μF to 0.1μF is usually suffi cient.
GND (Pin 2): Ground. Connect to a ground plane.
IN (Pin 3): Input Supply Voltage. The output load current
is supplied directly from IN. The IN pin should be locally
bypassed to ground if the LTC3025 is more than a few inches
away from another source of bulk capacitance. In general,
the output impedance of a battery rises with frequency, so
it is usually advisable to include an input bypass capacitor
when supplying IN from a battery. A capacitor in the range
of 0.1μF to 1μF is usually suffi cient.
OUT (Pin 4): Regulated Output Voltage. The OUT pin
supplies power to the load. A minimum ceramic output
BLOCK DIAGRAM
6
1
6
2
BIAS
SHDN
GND
SHDN
REFERENCE
0.4V
SOFT-START
capacitor of at least 1μF is required to ensure stability.
Larger output capacitors may be required for applications
with large transient loads to limit peak voltage transients.
See the Applications Information section for more informa-
tion on output capacitance.
ADJ (Pin 5): Adjust Input. This is the input to the error
amplifi er. The ADJ pin reference voltage is 0.4V referenced
to ground. The output voltage range is 0.4V to 3.6V and is
typically set by connecting ADJ to a resistor divider from
OUT to GND. See Figure 2.
SHDN (Pin 6): Shutdown Input, Active Low. This pin is
used to put the LTC3025 into shutdown. The SHDN pin
current is typically less than 10nA. The SHDN pin cannot
be left fl oating and must be tied to a valid logic level (such
as BIAS) if not used.
Exposed Pad (Pin 7): Ground and Heat Sink. Must be
soldered to PCB ground plane or large pad for optimal
thermal performance.
+
–
6 A
OUT
ADJ
IN
3025 BD
3
4
5
3025fa