ltc4268cdkd-1-trpbf Linear Technology Corporation, ltc4268cdkd-1-trpbf Datasheet - Page 21

• Manufacturer Part Number: ltc4268cdkd-1-trpbf
• Description: High Power Pd With Synchronous Noopto Flyback Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
The active high PWRGD pin features an internal,
open-collector output referenced to V
the active high PWRGD pin becomes valid when C1 reaches
–4V and pulls low until the load capacitor is fully charged.
At that point, PWRGD becomes high impedance, indicating
the switching regulator may begin running. The active
high PWRGD pin interfaces directly to the UVLO pin of
the LTC4268-1 with the aid of an external pull-up resistor
to Vcc. The PWRGD pin includes an internal 14V clamp to
V
becomes low impedance when V
PD UVLO turn-off threshold, then goes high impedance
when the V
range. Figure 11 shows a typical connection scheme for
the active high PWRGD pin.
The LTC4268-1 also includes an active low PWRGD pin
for system level use. PWRGD is referenced to the V
pin and when active will be near the V
negative rail (GND) of the internal switching regulator will
typically be referenced to V
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the switcher.
THERMAL PROTECTION
The LTC4268-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4268-1 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4268-1 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4268-1 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
NEG
. During a power supply ramp down event, PWRGD
PORT
voltages fall to within the detection voltage
NEG
and care must be taken to
PORT
drops below the 30V
PORTN
NEG
. During inrush,
potential. The
PORTN
example, if the PD input voltage steps from –37V to –57V,
the instantaneous power dissipated by the LTC4268-1 can
be as high as 16W. The LTC4268-1 protects itself from
damage by monitoring die temperature. If the die exceeds
the overtemperature trip point, the power MOSFET and
classifi cation transistors are disabled until the part cools
down. Once the die cools below the overtemperature
trip point, all functions are enabled automatically. During
classifi cation, excessive heating of the LTC4268-1 can
occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specifi cation requires a PD
to withstand application of any voltage from 0V to 57V
indefi nitely. To protect the LTC4268-1 in these situations,
the thermal protection circuitry disables the classifi cation
circuit and the input current if the die temperature exceeds
the overtemperature trip point. When the die cools down,
classifi cation and input current are enabled.
Once the LTC4268-1 has charged up the load capacitor and
the PD is powered and running, there will be some residual
heating due to the DC load current of the PD fl owing through
the internal MOSFET. In some high current applications,
the LTC4268-1 power dissipation may be signifi cant. The
LTC4268-1 uses a thermally enhanced DFN package that
includes an exposed pad which should be soldered to the
GND plane for heatsinking on the printed circuit board.
MAXIMUM AMBIENT TEMPERATURE
The LTC4268-1 I
disable the normal operating current limit. With the normal
current limit disabled, it is possible to pass currents
as high as 1.4A through the LTC4268-1. In this mode,
signifi cant package heating may occur. Depending on the
current, voltage, ambient temperature, and waveform
characteristics, the LTC4268-1 may shut down. To avoid
LIM_EN
pin allows the PD designer to
LTC4268-1
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