ltc4270 Linear Technology Corporation, ltc4270 Datasheet

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... The LTC4270/LTC4271 includes an I interface operable up to 1MHz. The LTC4270/LTC4271 is available in multiple power grades allowing delivered PD power up to 90W. L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks and LTPoE ++ is a trademark of Linear Technology Corporation ...

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... SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO, MID, GPn ........................DGND – 0. Operating Ambient Temperature Range LTC4271I..............................................–40°C to 85°C 2 Operating Ambient Temperature Range LTC4270I .............................................–40°C to 85°C – 0. 0.3V Junction Temperature (Note 2) ............................ 125°C EE Storage Temperature Range ......................–65 to 150°C Lead Temperature (Soldering, 10 sec) ................... 300° ...

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... EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB PART MARKING PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic QFN 4271 52-Lead (7mm × 8mm) Plastic QFN LTC4270A 52-Lead (7mm × 8mm) Plastic QFN LTC4270B 52-Lead (7mm × 8mm) Plastic QFN LTC4270C http://www.linear.com/leadfree/ http://www ...

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... LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER V Main PoE Supply Voltage EE Undervoltage Lock-Out V V Supply Voltage DD DD Undervoltage Lock-Out V Internal Regulator Supply Voltage CAP1 V Internal Regulator Supply Voltage CAP2 I V Supply Current Supply Resistance EE EE ...

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... V Short-Circuit Sense SC Port Current Readback Resolution LSB Weight Conversion Period Port Voltage Readback Resolution LSB Weight LTC4270 Die Temperature Die Temperature Offset Die Temperature LSB Weight Digital Interface V Digital Input Low Voltage ILD V Digital Input High Voltage IHD Digital Output Voltage Low ...

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... LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER XIO V XIO Digital Output Low OLX V XIO Digital Output High OHX XIO Digital Input Low Voltage XIO Digital Input High Voltage Internal Pull 4.3V EE PSE Timing Characteristics t Detection Time ...

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... MPS MPDO Note 9: Values Measured at V Note 10 fault condition occurs during an I will not be pulled down until a stop condition is present on the I Note 11: Load characteristics of the LTC4270 during Mark: 7V < (AGND – < 10V or I < 50μA. OUTn OUT ...

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... LTC4270/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af Power On Sequence in AUTO Pin Mode 0 AGND –10 FORCED CURRENT –20 DETECTION FORCED VOLTAGE –30 DETECTION VEE = –55V 802.3af –40 CLASS 3 PD CLASSIFICATION POWER ON –50 VEE –60 50ms/DIV 42701 G01 Powering Up into a 180μF Load AGND PORT VOLTAGE VEE = – ...

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... Pull Down GND PORT VOLTAGE 20V/DIV V EE GATE VOLTAGE 10V/DIV V EE FAULT PORT APPLIED CURRENT 500mA/DIV 0mA 42701 G13 LTC4270/LTC4271 Threshold CUT 664 656 = 0.25Ω 648 640 632 624 616 608 100 120 TEMPERATURE (°C) 42701 G10 225 PORT 1 ...

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... LTC4270/LTC4271 TEST TIMING DIAGRAMS V PORTn V INT Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes 10 t CLASSIFICATION DET FORCED- FORCED-CURRENT VOLTAGE MARK V CLASS t CLE t CLE PD CONNECTED t t PON V LIM V CUT SENSEn EE 0V INT Figure 2. Current Limit Timing ...

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... TEST TIMING DIAGRAMS SCL t 2 SDA GATEn t MSD MSD 42701 F04 Figure 4. Shut Down Delay Timing Figure Interface Timing LTC4270/LTC4271 42701 F05 42701f 11 ...

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... LTC4270/LTC4271 TIMING DIAGRAMS SCL SDA AD3 AD2 AD1 AD0 AD6 1 0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK A7 AD6 1 0 START BY ACK BY MASTER SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE 12 R/W ACK ...

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... R/W ACK AD6 1 0 AD3 AD2 AD1 AD0 ACK BY SLAVE FRAME 1 FRAME 2 ALERT RESPONSE ADDRESS BYTE SERIAL BUS ADDRESS BYTE Figure 9. Reading from Alert Response Address LTC4270/LTC4271 ACK NO ACK BY STOP BY MASTER MASTER 42701 F08 1 ACK NO ACK BY STOP BY MASTER MASTER 42701 F09 ...

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... Do not connect directly to V plane. See Layout Guide. EE Common Pins NC, DNC (LTC4271 Pins 7,13; LTC4270 Pins 42, 43, 44, 45, 46): All pins identified with “NC” or “DNC” must be left unconnected. LTC4271 AD0 (Pin 1): Address Bit 0. Tie the address pins high or low to set the starting I responds ...

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... DGND near the LTC4271 with at least a 0.1μF capacitor. RESET (Pin 14): Reset Input, Active Low. When the RESET pin is low, the LTC4270/LTC4271 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4271 begins normal operation ...

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... MOSFETs and increase system reliability in the event a single channel fails. All grades of the LTC4270/LTC4271 family offer advanced fourth generation PSE features, including per-port current monitoring, global temperature and V current policing, one second current averaging and four general purpose input/output pins ...

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... PSEs that support them) are known as Type 2. Older 13W 802.3af equipment is classified as Type 1. Type 1 PDs will work with all PSEs; Type 2 PDs may require Type 2 PSEs to work properly. The LTC4270/LTC4271 is designed to work in both Type 1 and Type 2 PSE de- signs, and also supports non-standard configurations at higher power levels. • ...

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... AUTO pin is high. In shutdown mode, the port is disabled and will not detect or power a PD. Regardless of which mode it is in, the LTC4270/LTC4271 will remove power automatically from any port that gener- ates a current limit fault. It will also automatically remove power from any port that generates a disconnect event if disconnect detection is enabled ...

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... Class 4 638mA The automatic setting of I and I CUT LIM if the LTC4270/LTC4271 is reset with the AUTO pin high. If the standalone application is a midspan, the MID pin should be tied high to enable correct midspan detection timing. DETECTION Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a real PD before applying power ...

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... Note that PDs in this range of capacitance are defined as invalid PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4270/LTC4271 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled on a per-port basis. ...

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... OUTn pin and measuring the resulting current; it then reports the discovered class in the Port Status register. If the LTC4270/LTC4271 is in AUTO pin mode, it will ad- ditionally use the classification result to set the I I thresholds ...

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... Power Status register (which implies that the first cycle found class 4), and Class 2 in the Port Status register. POWER CONTROL The primary function of the LTC4270/LTC4271 is to con- trol the delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET while monitoring the current via an external sense resistor and the output voltage at the OUT pin ...

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... LTC4270 SENSE pin to rise to an abnormally high voltage. A failed MOSFET may also 8A short from gate to drain, causing the LTC4270 GATE pin to rise to an abnormally high voltage ...

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... If a port is turned off via MSD, the corresponding Detection and Classification Enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. In the LTC4270/LTC4271 chipset the active level of MSD is register configurable as active high or low. The default is LTC4266-compatible active low behavior. Temperature and V ...

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... AD3-AD0 pins; this allows LTC4270/LTC4271s single bus. Ten LTC4270/ LTC4271 are equivalent to 30 quad PSEs or 120 ports. All LTC4270/LTC4271s also respond to the broadcast address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple LTC4270/ LTC4271s in a single transaction ...

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... V the LTC4270/LTC4271 to reset due to a UVLO fault. A 1μF , 100V X7R capacitor placed near the V electrolytic bulk capacitor of at least 47μF is recommended to minimize spurious resets ...

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... Port Output Cap Each port requires a 0.22μF cap across its outputs to keep the LTC4270 stable while in current limit during startup or overload. Common ceramic capacitors often have signifi- cant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended and must be located close to the PSE ...

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... AGND. The diodes at the ports EE steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the V capacitance. The surge suppressor has the additional benefit of protecting the LTC4270 from transients on the V supply. EE S1B diodes work well as port clamp diodes, and an SMAJ58A or equivalent is recommended for the V suppressor ...

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... TYPICAL APPLICATION LTC4270/LTC4271 42701f 29 ...

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... LTC4270/LTC4271 PACKAGE DESCRIPTION 4.50 0.05 2.45 0.05 (4 SIDES) 3.10 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH ...

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... DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE LTC4270/LTC4271 5.50 REF (2 SIDES 0.115 TYP ...

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... Single IEEE 802.3at PoE PSE Controller 2 LTC4311 SMBus Accelerator Linear Technology Corporation 32 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● XIO0 XIO1 CPA OUT12 GATE12 –54V SENSE12 LTC4270 CNA OUT1 DPA GATE1 SENSE1 RS –54V 0.25Ω, 1% DNA AGND V VSSK CAP2 EE 1μF D TSS ...