z16c32 ZiLOG Semiconductor, z16c32 Datasheet
z16c32
Available stocks
Related parts for z16c32
z16c32 Summary of contents
Page 1
... Oversampling; Break Detect and Generation; Odd, Even, Mark, Space or No Parity and Framing Error Detection. Supports 9-Bit and MIL-STD- 1553B Protocols. GENERAL DESCRIPTION The Z16C32 IUSC ™ (Integrated Universal Serial Controller multiprotocol datacommunications device with on- chip dual-channel DMA. The integration of a high-speed ...
Page 2
... Z ILOG GENERAL DESCRIPTION (Continued) There are additional reasons for using the Z16C32 IUSC than just reduced chip count and board space economy. The DMA and serial channel intercommunication offers application benefits as well. For example, events such as the reception of the end of a HDLC frame is internally communicated from the serial controller to the DMA so that each frame can be written into a separate memory buffer ...
Page 3
... Interface Transmit DMA Transmit Time Slot Assigner PS97USC0200 Interrupt Control FIFO Serial Clock Logic DPLL Transmitter Counters BRG0, BRG1 Figure 1. Z16C32 IUSC Block Diagram Z16C32 IUSC Receive DMA Receive FIFO Receiver I/O Time Slot Port Assigner 3 ™ ...
Page 4
... CLK /WAIT//RDY /RESET VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND Figure 2. Z16C32 Pin Functions Z16C32 IUSC ™ Serial Data Channel Clocks Channel I/O Channel DMA Interface Channel Interrupt Interface I/O Port System Clock Device Reset ...
Page 5
/UAS /INTACK R/W /WR /RD /DS /AS VCC VCC NC /RESET /CS D//C S//D /Wait//RDY 80 B// QFP 80 - Pin Figure 3. QFP 80-Pin Assignments P ...
Page 6
... AD6 AD7 GND VCC /RxREQ Figure 4. Z16C32 68-Pin PLCC Pin Assignments PIN DESCRIPTION Figure 2 shows the logical pin groupings of the IUSC’s pins, and Figure 3-4 shows the physical pin assignments. Only one strobe pin (/DS, /RD, /WR or Pulsed INTACK) should ever be active at one time. Any unused input pin (if an input when the IUSC is bus master or slave) must be pulled up to its inactive state ...
Page 7
... BCR write, chooses a multiplexed type of bus. Figure 5. BCR Reset Sequence and Bit Assignments PS97USC0200 Reset No /AS At Least One /AS BCR[2]=1 BCR[2]=0 BCR[15]=1 8-Bit With 8-Bit Without 16-Bit Separate Address Z16C32 IUSC Multiplexed Bus BCR[2]=0 BCR[2]=1 BCR[15]=0 16-Bit Separate Address ™ 7 ...
Page 8
... IUSC drives its IEO pin Low whenever its IEI pin is Low, and/or if the Under Service flag is set for any condition. This IUSC drives this signal slightly differently during an inter- rupt acknowledge cycle, in that it also forces IEO Low (has been) requesting an interrupt. Z16C32 IUSC ™ 8 ...
Page 9
... Clear to Send (input or output, active Low). Software can program the IUSC so that this signal enables/disables the transmitter. In addition, software can program the device to request interrupts in response to transitions on this line. The pin can also be used as a simple input or output. Z16C32 IUSC ™ PS97USC0200 ...
Page 10
... DMA transfer types, a flexible bus interface, and vectored interrupts. The architecture is described in three sections, DMA and Bus Interface Capabilities, Communi- cation between the DMA and Serial Channel, and Serial Communication Capabilities. The structure of the IUSC is shown in Figure 1. Z16C32 IUSC ™ 10 ...
Page 11
... Two pins are available as status signals of the type of transfer in progress. There are a variety of command and status registers to control and monitor the DMA channels. A DMA channel can be aborted with either the /ABORT pin or by software command. A pause command is also available to tempo- rarily suspend transfers. Z16C32 IUSC ™ PS97USC0200 ...
Page 12
... In the IUSC, the IP bit signals that an interrupt is pending IUS bit is set, this interrupt is being serviced and all interrupt sources of lower priority are prevented from requesting interrupts. An IUS bit is set during an interrupt acknowledge cycle if there are no higher priority devices requesting interrupts. Z16C32 IUSC ™ 12 ...
Page 13
... IUSC writes zeros as the status and count. Also, if the transmit channel needs to start a new memory buffer other than at the beginning of a frame, the DMA ignores the transmit control block. Z16C32 IUSC ™ PS97USC0200 ...
Page 14
... CPU and communicated to the other. This typically requires inter- rupts and the suspension of activity until status/control information is updated. This uses precious time and bus bandwidth, which can limit total throughput. Z16C32 IUSC Buffer 3 Address Buffer 3 Length Buffer 3 RSBR or 0 Buffer 3 RSHR or 0 ...
Page 15
... Bisync Mode. This mode is identical to monosync mode except that character synchronization requires two suc- cessive characters. The two characters need not be iden- tical. Z16C32 IUSC ™ PS97USC0200 ...
Page 16
... In both cases, there are transitions at the beginning of the bit cell to set up the level required to make the correct center transition Figure 6. Data Encoding Z16C32 IUSC ™ ...
Page 17
... The counters can be used as prescalers for the Baud Rate Generators. They also provide a stable transmit clock from a common source when the DPLL is providing the receive clock. The PORT0 and PORT1 pins can be used as inputs to the counters. Z16C32 IUSC ™ PS97USC0200 ...
Page 18
... Clock Multiplexers The clock multiplexer logic selects the receive and trans- mit clocks and optional outputs on the /RxC and/or /TxC pin(s). In the Z16C32, the PORT0 and PORT1 pins can be used directly as receive and transmit clocks, as well as being used as inputs to the counters. ...
Page 19
... Table reflects the state of AD5-AD1, AD13- AD9, CCAR5-CCAR1 or DCAR5-DCAR1 as applicable. The bit assignments of the registers are shown in Figures 8 through 81. See the IUSC Technical Manual for details. The register addressing is shown in Table 2 and the bit assignments for the registers are shown in Figure 7. Z16C32 IUSC ™ PS97USC0200 ...
Page 20
... BCR write, chooses a multiplexed type of bus. Figure 7. BCR Reset Sequence and Bit Assignments PS97USC0200 Reset No /AS At Least One /AS BCR[2]=1 BCR[2]=0 BCR[15]=1 8-Bit With 8-Bit Without 16-Bit Separate Address Z16C32 IUSC Multiplexed Bus BCR[2]=0 BCR[2]=1 BCR[15]=0 16-Bit Separate Address ™ 20 ...
Page 21
... TICR 11100 TSR 11101 TCLR 11110 TCCR 11111 TC1R Z16C32 IUSC Description Channel Command/Address Register Channel Mode Register Channel Command/Status Register Channel Control Register Port Status Register Port Control Register Test Mode Data Register Test Mode Control Register Clock Mode Control Register ...
Page 22
... RARL 10111 RARU 11101 NRBCR 11110 NRARL 11111 NRARU Z16C32 IUSC Description Bus Configuration Register DMA Command/Address Register Transmit DMA Channel Mode Register DMA Control Register DMA Array Count Register Burst Dwell Control Register DMA Interrupt Vector Register DMA Interrupt Control Register ...
Page 23
... Channel Select (WO) 0 Reserved 1 Reserved 0 Reserved 1 Reserved Channel Command Figure 8. DMA Command/Address Register D0 Upper//Lower Byte Select (WO) Address 0 (WO) Address 1 (WO) Address 2 (WO) Address 3 (WO) Address 4 (WO) Byte//Word Access (WO) Pointer Channel Select (WO) Master Bus Request Enable ** PS97USC0200 Z16C32 IUSC ™ ...
Page 24
... Reset Start Start/Continue (Buffered Mode Start/Continue (Other Than Buffered Mode Pause Abort Start/Init (Array or Linked Array Modes Start/Init (Normal or Buffered Modes) Z16C32 IUSC ™ Command 24 ...
Page 25
... Linked-Array Chained Figure 10. Tx/Rx DMA Mode Register (TDMR) (RDMR Increment Decrement Address Mode Fixed Address Reserved DMA Mode Z16C32 IUSC Software Abort (RO) Hardware Abort (RO) End of Buffer (RO) End of Array/Link (RO) Initialization (RO) Busy (RO) Get Link (RO) Continue (RO) 8-Bit Operand Enable Early T ermination ...
Page 26
... Channel Enabled, Data Transfer Phase Channel Disabled, Array Transfer Phase Channel Enabled, Array Transfer Phase Not Possible Channel Disabled, Link Transfer Phase Channel Enabled, Link Transfer Phase Not Possible Figure 11. Status Bit Combinations Z16C32 IUSC Buffered Mode Array-Chained Mode Linked Array-Chained Mode ™ 26 ...
Page 27
... End of Demand or Burst End of Demand Only DMA Request End of Burst Only Arbitration Reserved Channel Priority Figure 12. DMA Control Register (DCR) Z16C32 IUSC 32-bit Linear Reserved Addressing Segmented 16/16 Mode Segmented 8/24 /UAS Every Transaction One Wait Every Transaction Enable Transaction Status Bus Inactive Time ...
Page 28
... AD0 Figure 13. Array-Chained Bit Ordering Z16C32 IUSC AD0 AD0 ™ 28 ...
Page 29
... Figure 14b. Channel Array Count Bit Combinations Note: See the Z16C32 Technical Manual for the appropri- ate table with Linked Status Transfer feature enabled Getlink (in DCMR) Channel Array Count 3 Channel Array Count 2 ...
Page 30
... Bus transaction will always complete, even if the clock cycle limit is exceeded during the bus cycle, and even if the cycle is extended by external hardware signalling through /WAIT//RDY. PS97USC0200 Z16C32 IUSC Clock Cycle Limit (Bit 3) Clock Cycle Limit (Bit 4) Clock Cycle Limit (Bit 5) Clock Cycle Limit (Bit 6) ...
Page 31
... Address: 01100 (Shared) Figure 17. DMA Interrupt Control Register (DICR None 0 1 Not Used Type Code (RO Channel Channel Z16C32 IUSC ™ IV <0> IV <1> IV <2> IV <3> IV <4> IV <5> IV <6> IV <7> IV <0> (RO) IV <3> (RO) IV <4> (RO) IV <5> (RO) IV <6> (RO) IV <7> (RO ...
Page 32
... The format of this register is the same for the receiver and transmitter. The transmit register is accessed by addressing it with the D//C pin Low (0). The receive register is accessed by addressing it with the D//C pin High (1). This applies to Figures 20 through 26. PS97USC0200 Z16C32 IUSC Reset Tx IP (WO) Reset Rx IP (WO) Reserved Reset Tx IUS (WO) ...
Page 33
... Z ILOG CONTROL REGISTERS (Continued) Address: 10101 Figure 21. Tx/Rx Byte Count Register (TBCR)/(RBCR) Address: 10110 Figure 22. Tx/Rx Address Register (lower) (TARL)/(RARL Z16C32 IUSC ™ TTC <0> TTC <1> TTC <2> TTC <3> TTC <4> TTC <5> TTC <6> TTC <7> TTC <8> TTC <9> TTC <10> TTC <11> ...
Page 34
... Z ILOG Address: 10111 Figure 23. Tx/Rx Address Register (Upper) (TARU)/(RARU) Address: 11101 Figure 24. Next Tx/Rx Byte Counter Register (NTBCR)/(RTBCR) PS97USC0200 Z16C32 IUSC ™ TAR <16> TAR <17> TAR <18> TAR <19> TAR <20> TAR <21> TAR <22> TAR <23> TAR <24> TAR <25> TAR <26> TAR <27> TAR <28> TAR <29> ...
Page 35
... Z ILOG CONTROL REGISTERS (Continued) Address: 11110 Figure 25. Next Tx/Rx Address Register (Lower) (NTARL)/(RTARL) Address: 11111 Figure 26. Next Tx/Rx Address Register (Upper) (NTARU)/(RTARU Z16C32 IUSC ™ BAR <0> BAR <1> BAR <2> BAR <3> BAR <4> BAR <5> BAR <6> BAR <7> BAR <8> BAR <9> ...
Page 36
... Status Transfer Enabled is similar for Big and Little End Array. See Figure 27b. PS97USC0200 AD15 Buffer #1 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Buffer #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Buffer #3 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Dummy Ignored Ignored Z16C32 IUSC AD0 Ignored Ignored ™ 36 ...
Page 37
... CNT <15-8> RSB/TCB <15-8> RCHR/TCLR <15-8> 0 Buffer #2 AD<31-24> AD<15-8> CNT <15-8 > RSB/TCB <15-8> RCHR/TCLR <15-8> 0 Buffer #3 AD<31-24> AD<15-8> CNT <15-8> RSB/TCB <15-8> RCHR/TCLR <15-8> 0 Dummy Ignored Ignored Linked Frame Status Transfer Enabled Z16C32 IUSC AD0 AD<23-16> AD<7-0> CNT <7-0> RSB/TCB <7-0> RCHR/TCLR <7-0> 0 AD<23-16> AD<7-0> CNT <7-0> RSB/TCB <7-0> RCHR/TCLR <7-0> 0 AD<23-16> AD<7-0> CNT <7-0> RSB/TCB <7-0> RCHR/TCLR <7-0> 0 Ignored Ignored PS97USC0200 ...
Page 38
... After Termination Figure 28. Array-Chained, 16-Bit Bus, Little End Array PS97USC0200 AD15 Buffer #1 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Buffer #2 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Buffer #3 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Dummy Ignored Ignored Z16C32 IUSC AD0 Ignored Ignored ™ 38 ...
Page 39
... Status Transfer Enabled is similar for Big and Little End Array. See Figure 29b AD7 Buffer #1 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Buffer #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Dummy Ignored Ignored Ignored Ignored Z16C32 IUSC AD0 PS97USC0200 ™ ...
Page 40
... AD7 Buffer #1 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RSHR/TCLR <7-0> Buffer #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RSHR/TCLR <7-0> Dummy Linked Frame Status Transfer Enabled Z16C32 IUSC AD0 Ignored Ignored Ignored Ignored ™ 40 ...
Page 41
... Base Address Register After Termination Figure 30. Array-Chained, 8-Bit Bus, Little End Array AD7 Buffer #1 AD<7-0> AD<15-8> AD<23-16> AD<31-24> CNT<7-0> CNT<15-8> Buffer #2 AD<7-0> AD<15-8> AD<23-16> AD<31-24> CNT<7-0> CNT<15-8> Dummy Ignored Ignored Ignored Ignored Z16C32 IUSC AD0 PS97USC0200 ™ ...
Page 42
... Status Transfer Enabled is similar for Big and Little End Array. See Figure 31b. PS97USC0200 AD15 Buffer #1 AD<31-24> AD<23-16> AD<15-8> CNT<15-8> Base #2 AD<31-24> AD<23-16> AD<15-8> Buffer #2 AD<31-24> AD<23-16> AD<15-8> CNT<15-8> Base #3 AD<31-24> AD<23-16> AD<15-8> Buffer #3 AD<31-24> AD<23-16> AD<15-8> CNT<15-8> Base #n AD<31-24> AD<15-8> Buffer #n Ignored Ignored Z16C32 IUSC AD0 AD<7-0> CNT<7-0> AD<7-0> AD<7-0> CNT<7-0> AD<7-0> AD<7-0> CNT<7-0> AD<23-16> AD<7-0> Ignored Ignored ™ 42 ...
Page 43
... Figure 31b. Linked Array-Chained, 16-Bit Bus, Big End Array AD15 Buffer #1 AD<31-24> AD<23-16> AD <15-8> CNT<15-8> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RCHR/TCLR <7-0> 0 Base #2 AD<31-24> AD<23-16> AD <15-8> Buffer #2 AD<31-24> AD<23-16> AD <15-8> CNT<15-8> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RCHR/TCLR <7-0> 0 AD<31-24> AD<23-16> Base #3 AD <15-8> Buffer #3 AD<31-24> AD<23-16> AD <15-8> CNT<15-8> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RCHR/TCLR <7-0> 0 Z16C32 IUSC AD0 AD<7-0> CNT<7-0> 0 AD<7-0> AD<7-0> CNT<7-0> 0 AD<7-0> AD<7-0> CNT<7-0> 0 PS97USC0200 ™ ...
Page 44
... Figure 32. Linked Array-Chained, 16-Bit Bus, Little End Array PS97USC0200 AD15 Buffer #1 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Base #2 AD<15-8> AD<7-0> AD<31-24> AD<23-16> Buffer #2 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Base #3 AD<15-8> AD<7-0> AD<31-24> AD<23-16> Buffer #3 AD<15-8> AD<7-0> AD<31-24> AD<23-16> CNT<15-8> CNT<7-0> Base #n AD<15-8> AD<31-24> AD<23-16> Buffer #n Ignored Ignored Z16C32 IUSC AD0 AD<7-0> Ignored Ignored ™ 44 ...
Page 45
... Note: The addition of frame status/control information in the array with Linked Frame Status Transfer Enabled is similar to Big End Array. See Figure 33b AD7 Buffer #1 AD<7-0> AD<15-8> AD<23-16> AD<31-24> CNT<7-0> CNT<15-8> Base #2 AD<7-0> AD<15-8> AD<23-16> AD<31-24> Buffer #2 AD<7-0> AD<15-8> AD<23-16> AD<31-24> CNT<7-0> CNT<15-8> Base #3 AD<7-0> AD<15-8> AD<23-16> AD<31-24> Z16C32 IUSC AD0 PS97USC0200 ™ ...
Page 46
... Base Address + 9 #2 Base Address + 10 #2 Base Address + 11 Figure 33b. Linked Frame Status Transfer Enables PS97USC0200 AD7 Buffer #1 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RCHR/TCLR <7-0> Base #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> Buffer #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> RSB/TCB <15-8> RSB/TCB <7-0> RCHR/TCLR <15-8> RCHR/TCLR <7-0> Z16C32 IUSC AD0 ™ 46 ...
Page 47
... Base Address + 5 #2 Base Address + 6 #2 Base Address + 7 #2 Base Address + 8 #2 Base Address + 9 Figure 34. Linked Array-Chained 8-Bit Bus, Little End Array AD7 Buffer #1 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Base #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> Buffer #2 AD<31-24> AD<23-16> AD<15-8> AD<7-0> CNT<15-8> CNT<7-0> Base #3 AD<31-24> AD<23-16> AD<15-8> AD<7-0> Z16C32 IUSC AD0 PS97USC0200 ™ ...
Page 48
... Auto Echo Rx/ External Local Loopback Mode 1 1 Internal Local Loopback Channel Command (WO Z16C32 IUSC D0 Upper//Lower Byte Select (WO) Address 0 (WO) Address 1 (WO) Address 2 (WO) Address 3 (WO) Address 4 (WO) Byte//Word Access (WO) Channel Load DMA (WO) Rx/Tx Reset Selected * Upon Reset ™ 48 ...
Page 49
... Bisync 0 HDLC 1 Transparent Bisync Transmitter 0 NBIP Mode 1 802.3 0 Reserved 1 Reserved 0 Slaved Monosync 1 Reserved 0 HDLC Loop 1 Reserved Figure 36. Channel Mode Register (CMR) Z16C32 IUSC D0 0 Asynchronous 1 External Synchronous 0 Isochronous 1 Asynchronous with CV 0 Monosync 1 Bisync 0 HDLC 1 Transparent Bisync Receiver 0 NBIP Mode 1 802.3 0 Reserved ...
Page 50
... Data Rate 1 1 Reserved Transmitter 0 0 Asynchronous Mode Tx Clock Rate Tx Stop Bits Transmitter 0 1 Reserved Mode Z16C32 IUSC D1 D0 Receiver 0 0 Asynchronous Mode Rx Clock Rate Reserved Reserved D1 D0 Receiver 0 1 External Sync Mode Reserved Reserved ™ 50 ...
Page 51
... Transmitter 1 1 Asynchronous with CV Mode with Code Violation (MIL STD 1553 Receiver Isochronous Mode Reserved Reserved Tx Two Stop Bits Reserved D1 D0 Receiver 1 1 Asynchronous with CV Mode Rx Extended Word Reserved CV Polarity Tx Extended Word PS97USC0200 Z16C32 IUSC ™ ...
Page 52
... Transmitter 0 0 Monosync Mode Transmitter 0 1 Bisync Mode Tx Underrun Condition Z16C32 IUSC D1 D0 Receiver 0 0 Monosync Mode Rx Short Sync Character Rx Sync Strip Reserved Tx Short Sync Character Tx Preamble Enable Reserved Tx CRC on Underrun D1 D0 Receiver 0 1 Bisync Mode Rx Short Sync Character ...
Page 53
... Tx Underrun Condition Transmitter 1 1 Transparent Bisync Mode Tx Underrun Condition Z16C32 IUSC D0 Receiver 0 HDLC Mode Rx Address Search Mode Rx 16-Bit Control Rx Logical Control Enable Shared Zero Flags Tx Preamble Enable D0 Receiver 1 1 Transparent Bisync Mode EBCDIC Reserved EBCDIC Tx Preamble Enable PS97USC0200 ™ ...
Page 54
... NBIP Mode Tx Clock Rate Transmitter 0 1 802.3 Mode D1 D0 Receiver 0 0 NBIP Mode Rx Clock Rate Rx Parity on Data Reserved Tx Parity on Data Tx Address Bit D1 D0 Receiver 0 1 802.3 Mode Rx Address Search Reserved Reserved Tx CRC on Underrun Z16C32 IUSC ™ 54 ...
Page 55
... Slaved Monosync Mode Transmitter HDLC Loop Mode Tx Underrun Condition D0 Receiver 0 Reserved Mode Reserved Tx Short Sync Character Tx Active on Received Sync Reserved Tx CRC on Underrun Receiver Reserved Mode Reserved Shared-Zero Flags Tx Active on Poll PS97USC0200 Z16C32 IUSC ™ ...
Page 56
... Bits 0 Both Edges 1 Rising Edge Only DPLL Adjust/Sync Edge 0 Falling Edge Only 1 Adjust/Sync Inhibit Z16C32 IUSC Reserved HDLC Tx Last Character Length Counter By-pass Enable Loop Sending (RO) On Loop (RO) Clock Missed Latched/Unlatch 2 Clocks Missed Latched/Unlatch DPLL in Sync/Quick Sync RCC FIFO Clear (WO) ...
Page 57
... Alternating 0 and 1 8 Bits 16 Bits Tx Preamble 32 Bits Length 64 Bits Tx Control Block Transfer Figure 50. Channel Control Register (CCR) Z16C32 IUSC D1 D0 Reserved Wait for Rx DMA Trigger Rx Status Block Transfer Tx Shaved Bit Length (Async Only) (All Sync) Tx Flag Preamble Wait for Tx DMA Trigger PS97USC0200 ™ ...
Page 58
... Figure 51. Port Status Register (PSR) Z16C32 IUSC D0 /Port Bit 0 (RO) Port Bit 0 Latched/Unlatch /Port Bit 1 (RO) Port Bit 1 Latched/Unlatch /Port Bit 2 (RO) Port Bit 2 Latched/Unlatch /Port Bit 3 (RO) Port Bit 3 Latched/Unlatch /Port Bit 4 (RO) ...
Page 59
... Output 1 0 Tri-State Output 1 Rx Sync Output Port Bit 5 0 Output 0 Pin Control 1 Output 1 Port Bit 6 Pin Control Port Bit 7 Pin Control Figure 52. Port Control Register (PCR) Z16C32 IUSC Tri-State Output 0 1 CLK0 Input Port Bit Output 0 Pin Control 1 1 ...
Page 60
... Figure 53. Test Mode Data Register (TMDR Test Data <0> Test Data <1> Test Data <2> Test Data <3> Test Data <4> Test Data <5> Test Data <6> Test Data <7> Test Data <8> Test Data <9> Test Data <10> Test Data <11> Test Data <12> Test Data <13> Test Data <14> Test Data <15> Z16C32 IUSC ™ 60 ...
Page 61
... Figure 54. Test Mode Control Register (TMCR) Note: When software writes the value 1F to the LS byte of the Test Mode Control Register (TMCR), and then reads the Test Mode Data Register (TMDR), current versions of the Z16C32 will return hex 4453. Future revisions, if any, will return other values. 61 ...
Page 62
... CTR1 Output BRG0 Clock 1 0 /RxC Pin Source 1 1 /TxC Pin CTR0 Output CTR1 Output BRG1 Clock /RxC Pin Source /TxC Pin CTR0 Clock Source Z16C32 IUSC D0 0 Disabled 1 /RxC Pin 0 /TxC Pin 1 DPLL Output Receive Clock 0 BRG0 Output Source 1 BRG1 Output 0 ...
Page 63
... Disabled 1 NRZ/NRZI DPLL 0 Biphase-Mark/Space Divider 1 Biphase-Level DPLL Clock Divider Z16C32 IUSC BRG0 Enable BRG0 Single Cycle/Continuous Reserved BRG1 Enable BRG1 Single Cycle/Continuous Reserved Code Violations OK CTR1 Rate Match DPLL/CTR0 PS97USC0200 ™ ...
Page 64
... None 0 1 Device Status 1 0 I/O Status 1 1 Transmit Data Type 0 0 Transmit Status Code 0 1 Receive Data 1 0 Receive Status 1 1 Not Used Figure 57. Interrupt Vector Register (IVR) Z16C32 IUSC <0> IV <1> IV <2> IV <3> IV <4> IV <5> IV <6> IV <7> IV <0> (RO) IV <4> (RO) IV <5> (RO) IV <6> (RO) IV <7> (RO) ™ 64 ...
Page 65
... Output 0 Pin Control 1 1 Output 1 3-State Output Tx Request Output /TxREQ Output 0 Pin Control Output 1 /DCD Pin Control Figure 58. I/O Control Register (IOCR) Z16C32 IUSC D0 0 Input Pin 1 Rx Clock Output 0 Rx Byte Clock Output 1 SYNC Output /RxC Pin 0 BRG0 Output Control 1 BRG1 Output ...
Page 66
... Transmit Data and Above 0 0 Transmit Status and Above 0 1 Receive Data and Above 1 0 Receive Status Only 1 1 None Figure 59. Interrupt Control Register (ICR) Z16C32 IUSC D1 D0 Device Status IE I/O Status IE Transmit Data IE Transmit Status IE Receive Data IE Receive Status IE IE Command (WO) Reserved VIS Level ...
Page 67
... Null Command 0 1 Reset IP and IUS 1 0 Reset Set IP IUS Command (WO) Z16C32 IUSC D0 Device Status IP I/O Status IP Transmit Data IP Transmit Status IP Receive Data IP Receive Status IP IP Command (WO) Device Status IUS I/O Status IUS Transmit Data IUS Transmit Status IUS Receive Data IUS ...
Page 68
... Figure 61. Miscellaneous Interrupt Status Register (MISR) PS97USC0200 Z16C32 IUSC ™ BRG0 ZC Latched/Unlatch BRG1 ZC Latched/Unlatch DPLL SYNC Latched/Unlatch RCC Overflow Latched/Unlatch /CTS (RO) /CTS Latched/Unlatch /DCD (RO) /DCD Latched/Unlatch /TxREQ (RO) /TxREQ Latched/Unlatch /RxREQ (RO) ...
Page 69
... Arm 1 1 Both Edges Disabled /TxC Rising Edge Only Interrupt Falling Edge Only Arm Both Edges /RxC Interrupt Arm BRG0 ZC IA BRG1 ZC IA DPLL SYNC IA RCC Overflow IA /CTS Interrupt Arm /DCD Interrupt Arm /TxREQ Interrupt Arm PS97USC0200 Z16C32 IUSC ™ ...
Page 70
... Z ILOG Address: 1x000 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 63. Receive Data Register (RDR) Z16C32 IUSC D1 D0 RxDAT <0> (RO) RxDAT <1> (RO) RxDAT <2> (RO) RxDAT <3> (RO) RxDAT <4> (RO) RxDAT <5> (RO) RxDAT <6> (RO) RxDAT <7> (RO) RxDAT <8> (RO) RxDAT <9> (RO) RxDAT <10> (RO) RxDAT <11> (RO) RxDAT <12> (RO) RxDAT < ...
Page 71
... Type 1 1 Mark Rx CRC Polynomial Rx Data Decoding Figure 64. Receive Mode Register (RMR) 0 Disable Immediately 1 Disable After Reception Rx 0 Enable Without Auto-Enables Enable 1 Enable With Auto-Enables Rx Character Length Rx Parity Enable Abort Frame Status Rx CRC Enable Rx CRC Preset Value PS97USC0200 Z16C32 IUSC ™ ...
Page 72
... Reserved 1 1 Reserved 0 0 Reserved 0 1 Reserved 1 1 Reserved Z16C32 IUSC D0 Rx Character Available (RO) Rx Overrun Parity Error/Rx Frame Abort CRC/Framing Error (RO) Rx CV/EOT/EOF Rx Break/Abort Rx Idle Exited Hunt Short Frame/CV Polarity (RO) Residue Code 0 (RO) Residue Code 1 (RO) Residue Code 2 (RO) Receive ...
Page 73
... Z16C32 IUSC D0 TC0R Read Count/TC Rx Overrun IA Parity Error/Frame Abort IA Status on Words Rx CV/EOT/EOF IA Rx Break/Abort IA Rx Idle IA Exited Hunt IA Rx FIFO Control and Status (Fill/Interrupt/DMA Level) D0 TC0R Read Count/TC Rx Overrun IA Parity Error/Frame Abort IA Status on Words ...
Page 74
... Slots Slots (WO Slots Slots Slots Slots Slots Slots Slots Slot Offset (WO) Z16C32 IUSC D1 D0 TC0R Read Count/TC Rx Overrun IA Parity Error/Frame Abort IA Status on Words Rx CV/EOT/EOF IA Rx Break/Abort IA Rx Idle IA Exited Hunt IA 1 (WO) ™ 74 ...
Page 75
... Z ILOG CONTROL REGISTERS (Continued) Address: 10100 D15 D14 D13 D12 D11 D10 Figure 67. Receive Sync Register (RSR) Z16C32 IUSC RSYN <0> RSYN <1> RSYN <2> RSYN <3> RSYN <4> RSYN <5> RSYN <6> RSYN <7> RSYN <8> RSYN <9> RSYN <10> RSYN <11> ...
Page 76
... Z ILOG Address: 10101 D15 D14 D13 D12 D11 D10 D9 Figure 68. Receive Count Limit Register (RCLR) PS97USC0200 Z16C32 IUSC ™ D0 RCL <0> RCL <1> RCL <2> RCL <3> RCL <4> RCL <5> RCL <6> RCL <7> RCL <8> RCL <9> RCL <10> RCL <11> RCL <12> ...
Page 77
... Address: 10110 D15 D14 D13 D12 D11 D10 D9 Figure 69. Receive Character Count Register (RCCR Z16C32 IUSC ™ RCC <0> (RO) RCC <1> (RO) RCC <2> (RO) RCC <3> (RO) RCC <4> (RO) RCC <5> (RO) RCC <6> (RO) RCC <7> (RO) RCC <8> (RO) RCC <9> (RO) RCC <10> (RO) RCC <11> (RO) RCC <12> (RO) RCC < ...
Page 78
... Z ILOG Address: 10111 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 70. Time Constant 0 Register (TC0R) Z16C32 IUSC TC0 <0> TC0 <1> TC0 <2> TC0 <3> TC0 <4> TC0 <5> TC0 <6> TC0 <7> TC0 <8> TC0 <9> TC0 <10> TC0 <11> TC0 <12> TC0 <13> ...
Page 79
... Z ILOG CONTROL REGISTERS (Continued) Address: 1x000 D15 D14 D13 D12 D11 D10 Figure 71. Transmit Data Register (TDR) Z16C32 IUSC TxDAT <0> (WO) TxDAT <1> (WO) TxDAT <2> (WO) TxDAT <3> (WO) TxDAT <4> (WO) TxDAT <5> (WO) TxDAT <6> (WO) TxDAT <7> (WO) TxDAT <8> (WO) TxDAT <9> (WO) TxDAT <10> (WO) TxDAT < ...
Page 80
... Odd Tx Parity 1 0 Space Sense 1 1 Mark Tx CRC Type Tx Data Encoding Figure 72. Transmit Mode Register (TMR) Z16C32 IUSC D0 0 Disable Immediately 1 Disable After Transmission Tx 0 Enable Without Auto-Enables Enable 1 Enable With Auto-Enables Tx Character Length Tx Parity Enable Tx CRC on EOF/EOM Tx CRC Enable Tx CRC Start Value ™ ...
Page 81
... All Ones Reserved Alternating Mark and Space Space Mark Transmit Command (WO) Z16C32 IUSC Buffer Empty (RO) Tx Underrun All Sent (RO) Tx CRC Sent Tx EOF/EOT Sent Tx Abort Sent Tx Idle Sent Tx Preamble Sent Tx Idle Line Condition Reserved PS97USC0200 ™ ...
Page 82
... Z16C32 IUSC TC1R Read Count/TC Tx Overrun IA Wait for Send Command Tx CRC Sent IA Tx EOF/EOT Sent IA Tx Abort Sent IA Tx Idle Sent IA Tx Preamble Sent IA Tx FIFO Control and Status (Fill/Interrupt/DMA Level) D0 TC1R Read Count/TC Tx Underrun IA ...
Page 83
... Slots Slots Slots Slots Slots Slots Slot Offset (WO) Z16C32 IUSC D1 D0 TC1R Read Count/TC Tx Underrun IA Wait for Send Command Tx CRC Sent IA Tx EOF/EOT Sent IA Tx Abort Sent IA Tx Idle Sent IA Tx Preamble Sent IA 1 (WO) PS97USC0200 ™ ...
Page 84
... Z ILOG Address: 11100 D15 D14 D13 D12 D11 D10 D9 PS97USC0200 Figure 75. Transmit Sync Register (TSR) Z16C32 IUSC D1 D0 TSYN <0> TSYN <1> TSYN <2> TSYN <3> TSYN <4> TSYN <5> TSYN <6> TSYN <7> TSYN <8> TSYN <9> TSYN <10> TSYN <11> TSYN <12> TSYN <13> ...
Page 85
... CONTROL REGISTERS (Continued) Address: 11101 D15 D14 D13 D12 D11 D10 D9 Figure 76. Transmit Count Limit Register (TCLR Z16C32 IUSC D0 TCL <0> TCL <1> TCL <2> TCL <3> TCL <4> TCL <5> TCL <6> TCL <7> TCL <8> TCL <9> TCL <10> TCL <11> ...
Page 86
... ILOG Address: 11110 D15 D14 D13 D12 D11 D10 D9 Figure 77. Transmit Character Count Register (TCCR) PS97USC0200 Z16C32 IUSC D0 TCC <0> (RO) TCC <1> (RO) TCC <2> (RO) TCC <3> (RO) TCC <4> (RO) TCC <5> (RO) TCC <6> (RO) TCC <7> (RO) TCC <8> (RO) TCC <9> (RO) TCC <10> (RO) TCC <11> (RO) TCC <12> (RO) TCC < ...
Page 87
... D15 D14 D13 D12 D11 D10 Figure 78. Time Constant 1 Register (TC1R TC1 <0> TC1 <1> TC1 <2> TC1 <3> TC1 <4> TC1 <5> TC1 <6> TC1 <7> TC1 <8> TC1 <9> TC1 <10> TC1 <11> TC1 <12> TC1 <13> TC1 <14> TC1 <15> PS97USC0200 Z16C32 IUSC ™ ...
Page 88
... Bits 6-7 for Access Method Figure 79. Receive Status Block Register (RSBR) PS97USC0200 Z16C32 IUSC D0 RCC <0> Rx Overrun Parity Error Rx/Frame Abort CRC Error Rx Bound Short Frame/CV Polarity Residue Code 0 Residue Code 1 Residue Code 2 ...
Page 89
... Type 0 0 Status Acknowledge 0 1 Single Pulse Acknowledge 1 0 Reserved 1 1 Double Pulse Acknowledge 0 Tri-State All Pins Separate Address for 8-Bit Bus Z16C32 IUSC D0 Reserved HDLC Tx Last Character Length Reserved Tx Submode 0 Tx Submode 1 Tx Submode 2 Tx Submode 3 INTACK Mode * PS97USC0200 ™ ...
Page 90
... C sections of these specifications is not implied. Exposure to † C absolute maximum rating conditions for extended periods 2.2 W may affect device reliability. From Output Under Test Figure 82. Standard Test Load Min Max Z16C32 IUSC +5V 1.73 K 250 μ Unit Condition ™ 90 ...
Page 91
... Figure 83 through Figure 107. Min Typ Max 2.2 V +0.3 CC –0.3 0.8 2.4 V –0.8 CC 0.4 +10.00 +10. Figure 83. Reset Timing Figure 84. Bus Cycle Timing Note: /STB is any of the following: /DS, /RD, /WR or Pulsed /INTACK. Z16C32 IUSC Unit Condition –1 –250 μ +2 μA 0.4 < V < +2.4V IN μA 0.4 < V < ...
Page 92
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS R//W /DS AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 85. Multiplexed /DS Read Cycle Z16C32 IUSC ™ 92 ...
Page 93
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS R//W /DS AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 86. Multiplexed /DS Write Cycle Z16C32 IUSC ™ PS97USC0200 ...
Page 94
... Z ILOG /CS S//D, D//C /INTACK (Status) /AS /RD AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 87. Multiplexed /RD Read Cycle Z16C32 IUSC ™ 94 ...
Page 95
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /AS /WR AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 88. Multiplexed /WR Write Cycle Z16C32 IUSC ™ PS97USC0200 ...
Page 96
... Z ILOG /CS S//D, D//C /INTACK (Status) R//W /DS AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 89. Non-Multiplexed /DS Read Cycle Z16C32 IUSC ™ 96 ...
Page 97
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) R//W /DS AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 90. Non-Multiplexed /DS Write Cycle Z16C32 IUSC ™ PS97USC0200 ...
Page 98
... Z ILOG /CS S//D, D//C /INTACK (Status) /RD AD15-AD0 /RxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready) PS97USC0200 Figure 91. Non-Multiplexed /RD Read Cycle Z16C32 IUSC ™ 98 ...
Page 99
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /CS S//D, D//C /INTACK (Status) /WR AD15-AD0 /TxREQ /WAIT//RDY (Wait) /WAIT//RDY (Ready Figure 92. Non-Multiplexed /WR Write Cycle Z16C32 IUSC ™ PS97USC0200 ...
Page 100
... Z ILOG /AS /INTACK (Status) /DS AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 93. Multiplexed /DS Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 100 ...
Page 101
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /AS /INTACK (Status) /RD AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 94. Multiplexed /RD Interrupt Acknowledge Cycle 101 Z16C32 IUSC ™ PS97USC0200 ...
Page 102
... Z ILOG /AS /INTACK (Pulsed) AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 95. Multiplexed Pulsed Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 102 ...
Page 103
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (Status) /DS AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 96. Non-Multiplexed /DS Interrupt Acknowledge Cycle 103 Z16C32 IUSC ™ PS97USC0200 ...
Page 104
... Z ILOG /INTACK (Status) /RD AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) IEI IEO /INT Figure 97. Non-Multiplexed /RD Pulsed Interrupt Acknowledge Cycle PS97USC0200 Z16C32 IUSC ™ 104 ...
Page 105
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (Pulsed) AD15-AD0 /WAIT//RDY (Ready) IEI IEO /INT /WAIT//RDY (Wait) Figure 98. Non-Multiplexed Pulsed Interrupt Acknowledge Cycle 105 Z16C32 IUSC ™ PS97USC0200 ...
Page 106
... Z ILOG /AS /INTACK (2-Pulse) AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) IEI IEO /INT Figure 99. Multiplexed Double-Pulse Intack Cycle PS97USC0200 Z16C32 IUSC ™ 106 ...
Page 107
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) /INTACK (2-Pulse) AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) IEI IEO /INT Figure 100. Non-Multiplexed Double-Pulse Intack Cycle 107 Z16C32 IUSC ™ PS97USC0200 ...
Page 108
... Z ILOG CLK /UAS /AS /DS R//W /RD /WR S//D, D//C AD15-AD0 /BUSREQ /BIN PS97USC0200 Figure 101. DMA Start-Up Z16C32 IUSC ™ 108 ...
Page 109
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) CLK /UAS /AS /DS R//W /RD S//D, D//C AD15-AD0 /WAIT//RDY (Wait) /WAIT//RDY (Ready) /BIN /ABORT 109 Figure 102. Memory Read Z16C32 IUSC ™ PS97USC0200 ...
Page 110
... Z ILOG CLK /UAS /AS /DS R//W /WR S//D, D//C AD15-AD0 /WAIT//RDY (Ready) /WAIT//RDY (Wait) /BIN /ABORT PS97USC0200 Figure 103. Memory Write Z16C32 IUSC ™ 110 ...
Page 111
... Z ILOG AC CHARACTERISTICS Timing Diagrams (Continued) CLK /UAS /AS /DS R//W /RD /WR S//D, D//C AD15-AD0 111 Figure 104. Bus Release Z16C32 IUSC ™ PS97USC0200 ...
Page 112
... Z ILOG CLK /BUSREQ /BIN /BOUT PS97USC0200 Figure 105. Request Timing Z16C32 IUSC ™ 112 ...
Page 113
... Rise to /AS Fall Delay Time 42 TsDW(WR) Write Data to /WR Rise Setup Time 43 ThDW(WR) Write Data to /WR Rise Hold Time 44 TdWRf(TRQ) /WR Fall to /TxREQ Inactive Delay 113 Z16C32 IUSC Min Max Units Note 160 ...
Page 114
... Pulsed /INTACK Rise to /AS Fall Delay Time 100 TdPIA(DRa) Pulsed /INTACK Fall to Data Active Delay 101 TdPIA(DRn) Pulsed /INTACK Rise to Data Not Valid Delay 102 TdPIA(DRz) Pulsed /INTACK Rise to Data Float Delay PS97USC0200 Z16C32 IUSC Min Max Units Note [ ...
Page 115
... Read Data to /RD Rise Hold Time 144 TdCLK(ADD) CLK Rise to Direct Address Delay 145 TdCLK(AD) CLK Rise to Address Delay 146 ThAD(PC) Address to CLK Rise Hold Time 115 TdCLKf(DS) Z16C32 IUSC Min Max Units Note 200 ns ...
Page 116
... This is due to the internal timing paths unique to the Linked List Mode. The transmit and receive bit rates are not affected. [13] For Linked List Mode, the minimum for these values should be calculated using TwCLKh = 35 ns and TcCLK = 60 ns. Z16C32 IUSC Min Max Units Note ...
Page 117
... Z ILOG AC CHARACTERISTICS General Timing Diagram /RxC, /TxC Receive RxD /DCD as /SYNC External /TxC, /RxC Transmit TxD /RxC /TxC /CTS, /DCD /DCD as /SYNC Input 117 Figure 106. General Timing Z16C32 IUSC ™ PS97USC0200 ...
Page 118
... Cycle Time 12 TwTxCh /TxC High Width 13 TwTxCl /TxC Low Width 14 TcTxC /TxC Cycle Time 15 TwExT /DCD or /CTS Pulse Width 16 TWSY /DCD as /SYNC Input Pulse Width PS97USC0200 Z16C32 IUSC Min Max Units Note [1, [1,3] 0 ...
Page 119
... AC CHARACTERISTICS System Timing Diagram /RxC, /TxC Receive /RxREQ Request /RxC as Receiver Output /INT /RxC, /TxC Transmit /TxREQ /TxC as Transmitter Output /INT /CTS, /DCD, /TxREQ, /RxREQ /INT 119 Figure 107. Z16C32 System Timing Z16C32 IUSC ™ PS97USC0200 ...
Page 120
... Valid Delay Notes: [1] /RxC is /RxC or /TxC, whichever is supplying the receive clock. [2] /TxC is /TxC or /RxC, whichever is supplying the transmit clock. [3] Parameter applies only to FM encoding/decoding. PS97USC0200 Z16C32 IUSC Min Max Units Note 50 ns [2] ...
Page 121
... Z ILOG PACKAGE INFORMATION 121 68-Pin PLCC Package Diagram Z16C32 IUSC ™ PS97USC0200 ...
Page 122
... S = 0°C to 70°C Speed MHz Environmental C = Plastic Standard Example: Z 16C32 Z16C32, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc ...