ad74111 Analog Devices, Inc., ad74111 Datasheet
ad74111
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ad74111 Summary of contents
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... D/A conversion channel. The ADC channel provides >67 dB THD+N and the DAC channel pro- vides >88 dB THD+N, both over an audio signal bandwidth. The AD74111 is particularly suitable for a variety of applications where mono input and output channels are required, including audio sections of digital video camcorders, portable personal audio devices, and telematic applications ...
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... AD74111–SPECIFICATIONS Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Signal to Noise Ratio (SNR) Dynamic Range ( kHz, –60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Programmable Input Gain Gain Step Size Offset Error Full-Scale Input Voltage Input Resistance Input Capacitance ...
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... DVDD1 – 0.8 0 –10 DVDD1 – 0.4 0 –10 2.375 2.375 2.375 AVDD DVDD1 DVDD2 Current (mA) Current (mA) Current (mA) (Max)(mA) 6.11 (6.11) 0.15 (0.43) 0.72 (2.10) 3.80 (4.0) 0.15 (0.43) 0.85 (2.23) 0.60 (0.60) 0.15 (0.43) 0.27 (0.50) 8.60 0.15 (0.43) 1.72 (4.80) 0.035 0.15 (0.43) 0.49 (0.49) –3– AD74111 Typ Max Unit 21.5 kHz 0.2 mdB 5 kHz kHz dB µs 910 µs 87 21.5 kHz 10 mdB 5 kHz kHz dB µs 505 µs 55 DVDD1 V 0.8 V µA +10 10 ...
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... AD74111 TIMING CHARACTERISTICS Parameter MASTER CLOCK AND RESET t MCLK High MH t MCLK Low ML t RESET Low RES t DIN Setup Time RS t DIN Setup Time RH SERIAL PORT 2 t DCLK High DCLK Low CL t DFS Delay FD t DFS Setup Time FS t DFS Hold Time ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD74111 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Digital 2.5 V Power Supply Connection (Core) 15 DVDD1 Digital Power Supply Connection (Interface) 16 MCLK I External Master Clock Input PIN CONFIGURATION 16 DCLK MCLK 1 15 DIN DVDD1 2 14 DVDD2 DFS 3 AD74111 13 DGND DOUT 4 TOP VIEW (NOT TO SCALE) RESET 12 AGND 5 11 REFCAP AVDD 6 10 CAPP CAPN 7 9 VOUT ...
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... FREQUENCY – NORMALIZED TO TPC 2. ADC Composite Filter Response Low Group Delay Enabled 1.0 0.5 0 –0.5 –1.0 0 0.1 0.2 0.3 FREQUENCY – NORMALIZED TO TPC 3. ADC Composite Filter Response (Pass-Band Section) REV. 0 Typical Performance Characteristics–AD74111 0 –40 –80 –120 0.75 1 TPC 4. DAC Composite Filter Response 0 –40 –80 –120 0.75 1 ...
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... TPC 7. ADC THD+N vs. Sample Rate FUNCTIONAL DESCRIPTION General Description The AD74111 is a 2.5 V mono codec. It comprises an ADC and DAC channel with single-ended input and output. The ADC has a programmable gain stage and the DAC has programmable volume control. Each of these sections is described in further detail below ...
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... It is possible to bypass much of the digital filtering by enabling the Low Group Delay function in Control Register C. By reduc- ing the amount of filtering the AD74111 applies to input and output samples, the time delay between the sampling interval and when the sample is available is greatly reduced. This can be of benefit in applications such as telematics, where minimal time delays are important ...
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... V – 3 10%. /4 DVDD2 is the supply for the digital core of the AD74111 nominally a 2.5 V supply. Accessing the Internal Registers The AD74111 has seven registers that can be programmed to control the functions of the AD74111. Each register is 10 bits ...
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... DFS DIN *RESYNC IS ONLY USED WHEN THE DAC BECOMES In most cases easy to keep a DSP in synchronization with the AD74111 if they are both run from the same clock or the DSP clock is a multiple of the AD74111’s MCLK. In this case, –11– AD74111 MSB– ...
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... AD74111 there will be a fixed relationship between the instruction cycle time of the DSP program and the AD74111 timer could be used to accurately control the DAC updates timer is not available, the Multiframe-Sync (MFS) mode could be used to generate a DFS pulse every DCLKs, allowing the DSP to accurately control the number of DCLKs between updates using an autobuffering or DMA type technique ...
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... S DAC DATA (24 BITS) ADC DATA (24 BITS) 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) –13– AD74111 DAC DATA (24 BITS) ADC DATA (24 BITS) CONTROL (16 BITS) STATUS (16 BITS) CONTROL (16 BITS) STATUS (16 BITS) DAC DATA ...
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... AD74111 DAC DATA DIN (24 BITS) ADC DATA DOUT (24 BITS) DFS Figure 20. 32-Bit Data Mode, Word Length = 24 Bits DFS C DAC DIN S ADC DOUT DFS DAC DIN ADC DOUT DFS DIN C DAC DOUT S ADC 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) ...
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... Field. When this bit is low, a read of the register specified by the Address Field will occur at the next sample interval; the contents of the Data Field are ignored. 14–11 Register Address This 4-bit field is used to select one of the seven control registers of the AD74111. 10 Reserved This bit is reserved and should always be programmed with zero. 9– ...
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... AD74111 R/W ADDRESS RES Reserved 15 14, 13, 12 0000 0 0 R/W ADDRESS RES 15 14, 13, 12 0001 0 R/W ADDRESS RES 15 14, 13, 12 0010 0 R/W ADDRESS RES Multiframe Sync 15 14, 13, 12 0011 Normal Mode 1 = MFS Mode Table VI. Control Register A ADC Input ...
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... RES DAC Volume 14, 13, 12 0000000000 = 0 dBFS 0000000001 = (1023/1024) dBFS 0110 0 0000000010 = (1022/1024) dBFS 1111111110 = (2/1024) dBFS 1111111111 = Mute –17– AD74111 Function ADC DAC ADC Gain Mute Mute 000 = Normal 0 = Normal 001 = 3 dB ...
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... AD74111 16-Lead Thin Shrink Small Outline Package [TSSOP] 0.15 0.05 OUTLINE DIMENSIONS (RU-16) Dimensions shown in millimeters 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8 0.30 0.65 0 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AB –18– 0.75 0.60 0.45 REV. 0 ...
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