ad73411 Analog Devices, Inc., ad73411 Datasheet
ad73411
Related parts for ad73411
ad73411 Summary of contents
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... GENERAL DESCRIPTION The AD73411 is a single device incorporating a single analog front end (AFE) and a microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The AD73411’s analog front end (AFE) section is suitable for general-purpose applications including speech and telephony. ...
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... AD73411–SPECIFICATIONS Parameter AFE SECTION REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) ...
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... V 3.0 3 –20°C and T = +85°C. MIN MAX 11 )/DMCLK. AD73411 Test Conditions/Comments Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave kHz; Interpolator Bypassed SAMP kHz SAMP PGA = 6 dB |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA ...
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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR. 9 Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND and 3 V. For typical figures for supply currents, refer to Power Dissipation section. ...
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... AD73411 Test Conditions REFOUT Disabled REFOUT Disabled REFOUT Disabled MCLK Active Levels Equal and DVDD Digital Inputs Static and Equal DVDD Description See Figure 1 16.384 MHz AMCLK Period ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73411 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Combined Memory Select Output (Output) Memory Read Enable Output (Output) Memory Write Enable Output. IRQ2/ (Input) Edge- or Level-Sensitive Interrupt Request PF7 D1 (Input/Output) Programmable I/O Pin. IRQL1/ (Input) Level-Sensitive Interrupt Requests C1 (Input/Output) Programmable I/O Pin. PF6 PBGA BALL FUNCTION DESCRIPTIONS AD73411 ...
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... AD73411 PBGA BALL FUNCTION DESCRIPTIONS (Continued) BGA Mnemonic Location Function IRQL0/ (Input) Level-Sensitive Interrupt Requests B1 (Input/Output) Programmable I/O Pin. PF5 IRQE/ (Input) Edge-Sensitive Interrupt Requests A1 (Input/Output) Programmable I/O Pin. PF4 H4 (Input/Output) Programmable I/O Pin During Normal Operation. PF3 (Input) Mode Select Input—Checked Only During RESET. ...
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... ADC DAC ANALOG FRONT END SECTION Figure overall block diagram of the AD73411. The pro- cessor section contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units directly process 16-bit data and have provi- sions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations ...
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... ADC and DAC. Both ADC and DAC share a common reference whose nominal value is 1.2 V. Figure 2 shows a block diagram of the AFE sec- tion of the AD73411. It shows an ADC and DAC as well as a common reference. Communication to both channels is handled by the SPORT2 block which interfaces to either SPORT0 or SPORT1 of the DSP section ...
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... S DMCLK/16 Decimation Filter The digital filter used in the AD73411 carries out two impor- tant functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high-frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter that ...
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... MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec’s on-chip voltage reference. Voltage Reference The AD73411 reference, REFCAP bandgap reference that provides a low noise, temperature-compensated reference to the DAC and ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to bias other external analog circuitry ...
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... The SPORT block diagram, shown in Figure 6, details the six control registers (A–F), external MCLK to internal DMCLK divider, and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73411 features a master clock divider that allows users the flexibility of dividing externally available high-frequency DSP or CPU clocks to gen- ...
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... CONTROL REGISTER A Sample Rate Divider The AD73411 features a programmable sample rate divider that allows users flexibility in matching the codec’s ADC and DAC sample rates to the needs of the DSP software. The maximum sample rate available is DMCLK/256, which offers the lowest conversion group delay, while the other available rates are: DMCLK/512, DMCLK/1024, and DMCLK/2048 ...
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... If the address is not zero decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the five control registers on the AD73411. This 8-bit field holds the data that written to or read from the selected register provided the address fi ...
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... AD73411 CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C 7 RES Bit CONTROL REGISTER D 7 MUTE Bit Table X. Control Register B Description MCD2 MCD1 MCD0 SCD1 Name Description DIR0 ...
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... Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) SEEN Single-Ended Enable (0 = Disabled Enabled) INV Input Invert (0 = Disabled Enabled) ALB Analog Loopback of Output to Input (0 = Disabled Enabled) AD73411 1 0 DA1 DA0 1 0 RES RES ...
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... AD73411 AFE Operating Modes Five operating modes are available on the AFE. Two of these— Digital Loop-Back and Sport Loop-Back—are provided as diagnostic modes with the other three, Program, Data and Mixed Program/Data, being available for general-purpose use. The device configuration—register settings—can be changed only in Program, and Mixed Program/Data Modes ...
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... DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SAMPLE WORD (DEVICE 2) SDOFS(1) SDIFS(2) SDO(1) SAMPLE WORD (DEVICE 1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 1) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 2) DATA (CONTROL) WORD (DEVICE 1) AD73411 ...
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... TIME Cascade Operation AD73411 The AD73411 has been designed to support up to eight codecs in a cascade connected to a single serial port. The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hardware overhead for control signals or addressing ...
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... BUS BYTE DMA Program memory can store both instructions and data, permitting CONTROLLER the AD73411 to fetch two operands in a single cycle, one from OR program memory and one from data memory. The AD73411 EXTERNAL DATA can fetch an operand from program memory and the next in- BUS struction in the same cycle ...
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... See Pin Function Descriptions section. Memory Interface Pins The AD73411 processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full exter- nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capa- bilities ...
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... The High or Low power-down interrupt is nonmaskable. Float Input = High or Low, The AD73411 masks all interrupts for one instruction cycle Output = Float following the execution of an instruction that modifies the High or Low IMASK register. This does not affect serial port autobuffering High or Low or DMA transfers ...
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... Clock Signals The AD73411 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during opera- tion, or operated below the specified frequency during normal operation ...
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... Reset BYTE D MEMORY 15–8 The RESET signal initiates a master reset of the DSP section of DATA the AD73411. The RESET signal must be asserted during the CS A power-up sequence to assure proper initialization. RESET during 10–0 ADDR I/O SPACE initial power-up must be held long enough to allow the internal ...
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... Between 0x2000 control registers. The AD73411-80 has 16K words on Data and 0x3FFF Memory RAM on-chip (the AD73411-40 has 8K words on Data Memory RAM on-chip), consisting of 16,352 user-accessible locations in the case of the AD73411-80 (8,160 user-accessible locations in the case of the AD73411-40) and 32 memory- mapped registers ...
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... Boot Memory Select (BMS) Disable 8K INTERNAL DMOVLAY = 0 OR The AD73411 also lets you boot the processor from one exter- EXTERNAL 8K DMOVLAY = 1, 2 nal memory space while using a different external memory space 0 x 0000 for BDMA transfers during normal operation. You can use the CMS to select the fi ...
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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the AD73411. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the DSP’ ...
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... IDMA Port Booting The AD73411 can also boot programs through its Internal DMA port. If Mode Mode and Mode the AD73411 boots from the IDMA port. IDMA feature can load as much on- chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to ...
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... RESET GND The EZ-ICE uses the EE (emulator enable) signal to take control of the AD73411 in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. ...
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... SE Cascade Operation Where it is required to configure extra analog I/O channels to the existing two channels on the AD73411 possible to cascade up to seven more channels (using single channel AD73311 or dual channel AD73322 AFEs) by using the scheme described in Figure 24 necessary, however, to ensure that the timing of the SE and ARESET signals is synchronized at each device in the cascade. A simple D-type flip-flop is suffi ...
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... If the ADC is being connected in single-ended mode, the AD73411 should be programmed for single-ended mode using the SEEN and INV bits of CRF, and the inputs connected as shown in Figure 28. When operated in single-ended input mode, the AD73411 can multiplex one of the two inputs to the ADC input, as shown in Figures 28 and 29. VINP VINN ...
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... In this circuit the AD73411 input channel is being used in single-ended mode where the inverting amplifier provides suitable gain to scale the input signal relative to the ADC’ ...
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... However, because the resolution of the AD73411’s ADC is high, and the noise levels from the AD73411 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD73411 should be designed so the analog and digital sections are separated and confi ...
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... SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPORT2 Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sample Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Resetting the AFE Section of the AD73411 . . . . . . . . . . . 14 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AFE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 18 Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sport Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog Loop-Back ...
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... AD73411 0.089 (2.27) 0.073 (1.85) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 119-Ball Plastic Ball Grid Array (PBGA) B-119 0.300 (7.62) BSC 0.559 (14.20) BOTTOM 0.543 (13.80) VIEW 0.050 0.874 (22.20) (1.27) TOP VIEW BSC 0.858 (21.80) 0.033 (0.84) REF 0.050 (1.27) 0.126 (3.19) REF DETAIL A DETAIL A 0.028 (0.70) 0.020 (0.50) ...