ics84330c Integrated Device Technology, ics84330c Datasheet - Page 4

• Manufacturer Part Number: ics84330c
• Description: 700mhz, Low Jitter, Crystal-to-3.3v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

Function Tables
Table 3A. Parallel and Serial Mode Function Table
NOTE: L = LOW
Table 3B. Programmable VCO Frequency Function Table
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
nP_LOAD
ICS84330C
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VCO Frequency
X
H
H
H
H
H
L
↑
(MHz)
250
252
254
256
696
698
700
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
N1
•
•
0
0
1
1
Data
Data
M
X
X
X
X
X
X
Inputs
Data
Data
N
X
X
X
X
X
X
M Divide
125
126
127
128
348
349
350
•
•
S_LOAD
Inputs
N0
0
1
0
1
X
X
↑
↓
H
L
L
L
256
M8
0
0
0
0
1
1
1
•
•
S_CLOCK
N Divider Value
X
X
X
↑
X
L
L
↑
128
M7
0
0
0
1
0
0
0
•
•
2
4
8
1
S_DATA
Data
Data
Data
Data
X
X
X
X
M6
64
1
1
1
0
1
1
1
•
•
4
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA
on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Minimum
M5
32
1
1
1
0
0
0
0
•
•
31.25
62.5
125
250
Output Frequency (MHz)
M4
16
1
1
1
0
1
1
1
•
•
M3
Maximum
8
1
1
1
0
1
1
1
•
•
ICS84330CV REV. C JANUARY 28, 2009
87.5
350
175
700
M2
4
1
1
1
0
1
1
1
•
•
M1
2
0
1
0
1
0
0
1
•
•
M0
1
1
0
1
0
0
1
0
•
•