ics8535-21 Integrated Device Technology, ics8535-21 Datasheet

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ics8535-21

Manufacturer Part Number
ics8535-21
Description
Low Skew, 1-to-2 Lvcmos/lvttl-to-3.3v Lvpecl Fanout Buffer
Manufacturer
Integrated Device Technology
Datasheet
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-
3.3V LVPECL CLOCK GENERATOR
General Description
single-ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock enable is
internally synchronized to eliminate runt clock pulses on the output
during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8535-21 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
CLK_SEL
HiPerClockS™
CLK_EN
ICS
CLK0
CLK1
Pullup
Pulludown
Pulludown
Pulludown
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT. The
ICS8535-21 has two single-ended clock inputs. The
0
1
D
LE
Q
Q0
Q0
Q1
Q1
1
Features
4.40mm x 5.0mm x 0.925mm package body
Pin Assignment
Two differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
ICS8535-21 14 Lead TSSOP
CLK_SEL
CLK_EN
CLK0
CLK1
V
V
V
EE
CC
EE
G Package
Top View
1
2
3
4
5
6
7
ICS8535AG-21 REV. A FEBRUARY 24, 2009
14
13
12
11
10
9
8
V
Q0
Q0
nc
Q1
Q1
V
CC
CC
ICS8535-21

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ics8535-21 Summary of contents

Page 1

... LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO- 3.3V LVPECL CLOCK GENERATOR General Description The ICS8535- low skew, high performance ICS 1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of HiPerClockS™ High Performance Clock Solutions from IDT. The ICS8535-21 has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3 ...

Page 2

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Power EE 2 CLK_EN Input 3 CLK_SEL Input 4, 6 CLK0, CLK1 Input Power Q1, Q1 Output 11 nc Unused 12, 13 Q0, Q0 Output NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ...

Page 3

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs CLK_EN CLK_SEL After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B. ...

Page 4

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability ...

Page 5

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Table 4C. LVPECL DC Characteristics, V Symbol Parameter V Output High Current; NOTE Output Low Current; NOTE Peak-to-Peak Output Voltage Swing SWING NOTE 1: Outputs termination with 50Ω Electrical Characteristics Table 5. AC Characteristics Parameter Symbol ...

Page 6

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications ...

Page 7

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Parameter Measurement Information LVPECL V EE 1.3V ± 0.165V - 3.3V LVPECL Output Load AC Test Circuit tsk(o) Output Skew 80% Clock 20% Outputs t R Output Rise/Fall Time IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER Par SCOPE ...

Page 8

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Application Information Recommendations for Unused Input and Output Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. ...

Page 9

... VCC VCC 8535-21 (U1-7) (U1-8) VCC .1uF .1uF 10uf Figure 3. ICS8535-21 LVPECL Buffer Schematic Example IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER pin. For ICS8535-21, the unused clock outputs can be left floating. (U1-14) C4 .1uF Vcco = 3. ...

Page 10

... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...

Page 11

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure Figure 4. LVPECL Driver Circuit and Termination T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – ...

Page 12

... Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS8535-21 is: 412 Package Outline and Package Dimension Package Outline - G Suffix for 14 Lead TSSOP IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER θ ...

Page 13

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number Marking 8535AG-21 8535AG21 8535AG-21T 8535AG21 8535AG-21LF 8535A21L 8535AG-21LFT 8535A21L NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ...

Page 14

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change 1 Features Section - added lead-free bullet Added Recommendations for Unused Input and Output Pins Ordering Information Table - added lead-free part number, marking and note Ordering Information Table - added lead-free marking ...

Page 15

... ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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