ics8305i Integrated Device Technology, ics8305i Datasheet
ics8305i
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ics8305i Summary of contents
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... Outputs are forced LOW when the clock is disabled. A sepa- rate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well de- fined performance and repeatability ...
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... TSD B UFFER REV. B MAY 19, 2005 ICS8305I ...
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... Enabled D IAGRAM / TSD B UFFER REV. B MAY 19, 2005 ICS8305I ...
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... µ µ A µ A µ µ µ REV. B MAY 19, 2005 ICS8305I ...
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... µ A µ A µ REV. B MAY 19, 2005 ICS8305I ...
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... REV. B MAY 19, 2005 ICS8305I ...
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... The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html ULTIPLEXED IFFERENTIAL B ANOUT UFFER Input/Output Additive Phase Jitter at 155.52MHz = 0.04ps typical 10M 100M ( REV. B MAY 19, 2005 / TSD ICS8305I ...
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... ULTIPLEXED IFFERENTIAL -LVCMOS/LVTTL F TO ANOUT I NFORMATION 1.25V±5% V DDO Qx GND -1.25V±5% /2. ORE UTPUT OAD EST V Cross Points NPUT EVEL V DDO 2 V DDO 2 tsk(pp ART KEW / TSD B UFFER SCOPE IRCUIT V CMR REV. B MAY 19, 2005 ICS8305I ...
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... IDT™ / ICS™ LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER KEW LVCMOS- Clock Outputs O UTPUT V DDO 2 x 100% /P IDTH ERIOD www.icst.com/products/hiperclocks.html - ULTIPLEXED IFFERENTIAL -LVCMOS/LVTTL F TO ANOUT 80% 80% 20 ISE ALL IME / TSD B UFFER 20% REV. B MAY 19, 2005 ICS8305I ...
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... R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input V_REF C1 0. IGURE INGLE NDED IGNAL RIVING www.icst.com/products/hiperclocks.html - ULTIPLEXED IFFERENTIAL -LVCMOS/LVTTL F TO ANOUT EVELS = 3.3V, V_REF should be 1.25V DD CLK nCLK D I IFFERENTIAL NPUT / TSD B UFFER REV. B MAY 19, 2005 ICS8305I ...
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... 3B CLK/ CLK LOCK N NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 3D CLK/ CLK LOCK N NPUT 3.3V LVDS D RIVER / TSD B UFFER Input D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY REV. B MAY 19, 2005 ICS8305I ...
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... LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER Systems, Inc CHEMATIC XAMPLE This application note provides general design guide using ICS8305I LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305I LVCMOS clock buffer. In this example, the input VDD VDD ...
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... Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html - ULTIPLEXED IFFERENTIAL -LVCMOS/LVTTL F ANOUT ° REV. B MAY 19, 2005 / TSD B UFFER ICS8305I ...
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... R / IFFERENTIAL TSD B UFFER ° ° ° ° ° ° ° ° REV. B MAY 19, 2005 ICS8305I ...
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... TSD B UFFER REV. B MAY 19, 2005 ICS8305I ...
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... ICS8302-01 ICS1890 ICS1527 ICS8305I MK1491-14 ICS280 Video Clock Synthesizer LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER Auto-Negotiation Advertisement Register (register 4 [0x04]) LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT OPTi ACPI Firestar Clock Source TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks ...