ics9ums9610 Integrated Device Technology, ics9ums9610 Datasheet
ics9ums9610
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ics9ums9610 Summary of contents
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... MLF, 6x6 mm, 0.4mm pitch * indicates inputs with internal pull up of ~10Kohm to 1.5V 1 DATASHEET ICS9UMS9610 Supports Dothan ULV CPUs with 100 to 200 MHz CPU outputs Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins CPU STOP# input for power manangment ...
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... ICS9UMS9610 PC MAIN CLOCK Pin Description PIN # PIN NAME TYPE 1 CPU_STOP#_3.3 IN This active-low input stops all CPU clocks that are set to be stoppable. This level sensitive strobe determines when latch inputs are valid and are 2 CLKPWRGD#/PD_3.3 IN ready to be sampled. When high, this asynchronous input places the device into the power down state ...
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... ICS9UMS9610 PC MAIN CLOCK Pin Description (continued) PIN # PIN NAME TYPE 25 GNDSRC GND Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with 26 SRCC0_LPR OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm ...
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... ICS9UMS9610 PC MAIN CLOCK Funtional Block Diagram Power Groups Pin Number Description VDD GND 41, 46 Low power outputs 40, 45 CPUCLK 42 VDDCORE_1.5V 30 Low power outputs 25, 33 SRCCLK 29 VDDCORE_1.5V 22 Low power outputs 19 LCDCLK 23 VDDCORE_1.5V 15 Low power outputs 18 DOT 96Mhz 14 VDDCORE_1.5V Xtal, REF IDT ...
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... ICS9UMS9610 PC MAIN CLOCK Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Supply Voltage VDDxxx_3.3 1.5V Supply Voltage VDDxxx_1.5 3.3_Input High Voltage V 1.5_Input High Voltage V Minimum Input Voltage V Storage Temperature Ts Input ESD protection ESD prot Notes: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied, nor guaranteed. ...
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... ICS9UMS9610 PC MAIN CLOCK AC Electrical Characteristics - Input/Common Parameters PARAMETER SYMBOL Clk Stabilization T STAB Tdrive_PD# T DRPD Tdrive_CPU T DRSRC Tfall_PD# T Trise_PD Electrical Characteristics - Low Power Differential Outputs PARAMETER SYMBOL Rising Edge Slew Rate t Falling Edge Slew Rate t Rise/Fall Time Variation t SLVAR Maximum Output Voltage ...
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... ICS9UMS9610 PC MAIN CLOCK Electrical Characteristics - SMBus Interface PARAMETER SYMBOL SMBus Voltage V Low-level Output Voltage V OLSMB Current sinking at I PULLUP V = 0.4 V OLSMB SCLK/SDATA T Clock/Data Rise Time SCLK/SDATA T Clock/Data Fall Time Maximum SMBus Operating F SMBUS Frequency Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. ...
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... ICS9UMS9610 PC MAIN CLOCK Table 1: CPU Frequency Select Table CPU SRC MHz MHz 0 0 133. 166.67 100. 100. 200. low-threshold input.Please see V L the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. ...
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... ICS9UMS9610 PC MAIN CLOCK 2 General I C serial interface information for the ICS9UMS9610 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 0 PLL & Divider Enable Register Bit(s) Pin # Name 7 - PLL1 Enable 6 - PLL2 Enable 5 - PLL3 Enable 4 - CPU Divider 3 - Enable SRC Output 2 - Divider Enable LCD Output 1 - Divider Enable DOT Output 0 - Divider Enable Byte 1 PLL SS Enable/Control Register Bit(s) Pin # Name 7 PLL1 SS Enable ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 2 Output Enable Register Bit(s) Pin # Name 7 CPU0 Enable 6 CPU1 Enable 5 CPU2 Enable 4 SRC0 Enable 3 SRC1 Enable 2 SRC2 Enable 1 DOT Enable 0 LCD100 Enable Byte 3 Output Control Register Bit(s) Pin # Name 7 Reserved 6 Reserved 5 REF Enable 4 REF Slew 3 CPU0 Stop ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 4 CPU PLL M/N Register Bit(s) Pin # Name CPU N Div8 Bit 7 CPU N Div9 Bit 6 CPU M Div5 Bit 5 CPU M Div4 Bit 4 CPU M Div3 Bit 3 CPU M Div2 Bit 2 CPU M Div1 Bit 1 Bit 0 CPU M Div0 Byte 5 CPU PLL M/N Register Bit(s) Pin # Name ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 8 LCD100 PLL M/N Register Bit(s) Pin # Name LCD100 N Div8 Bit 7 LCD100 N Div9 Bit 6 Bit 5 LCD100 M Div5 Bit 4 LCD100 M Div4 Bit 3 LCD100 M Div3 Bit 2 LCD100 M Div2 Bit 1 LCD100 M Div1 Bit 0 LCD100 M Div0 Byte 9 LCD100 PLL M/N Register Bit(s) Pin # Name ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 12 Device ID Register Bit(s) Pin # Name 7 DEV_ID3 6 DEV_ID2 5 DEV_ID1 4 DEV_ID0 3 Reserved 2 Reserved 1 Reserved 0 Reserved Byte 13 Reserved Register Bit(s) Pin # Name Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Bit 3 Reserved Bit 2 Reserved Reserved Bit 1 Bit 0 Reserved Byte 14 Reserved Register ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 16 M/N Enable Register Bit(s) Pin # Name MN Enable Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Byte 17 CPU PLL Spread Spectrum Index Register Bit(s) Pin # Name Bit 7 CPUSSP7 Bit 6 CPUSSP6 Bit 5 CPUSSP5 ...
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... ICS9UMS9610 PC MAIN CLOCK Byte 20 LCD100 PLL Spread Spectrum Index Register Bit(s) Pin # Name Bit 7 LCDSSP15 Bit 6 LCDSSP14 Bit 5 LCDSSP13 Bit 4 LCDSSP12 Bit 3 LCDSSP11 Bit 2 LCDSSP10 Bit 1 LCDSSP9 Bit 0 LCDSSP8 Byte 21 CPU PLL M/N Register Bit(s) Pin # Name CPU NDIV 10 Bit 7 CPU NDIV 11 ...
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... ICS9UMS9610 PC MAIN CLOCK Test Clarification Table Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode TEST_MODE -->low Vth input TEST_MODE is a real time input TM M IDT /ICST PC MAIN CLOCK HW TEST_SEL TEST_MODE OUTPUT HW PIN HW PIN <0.35V X NORMAL >0.7V <0.35V HI-Z >0.7V >0.7V REF/N 17 1336— ...
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... ICS9UMS9610 PC MAIN CLOCK MLF Top Mark Information (9UMS9610) Line 1. Company name Line 2. Part Number Line 3. YYWW = Date Code Line 3. Country of Origin Line 4. ####### = Lot Number TM M IDT /ICST PC MAIN CLOCK ICS UMS9610yL 6 YYWW ...
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... ICS9UMS9610 PC MAIN CLOCK Index Area N Top View D Chamfer 4x 0.6 x 0.6 max OPTIONAL DIMENSIONS SYMBOL MIN 0.20 Reference b 0.18 e 0.40 BASIC Ordering Information Order Num ber Ma rking 9UMS9610CKLF see page 18 9UMS9610CKLFT Par ts that ar e orde ith a "LF" s uffix to the part num be r are the Pb- configuration and ar e RoHS com pliant. ...
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... ICS9UMS9610 PC MAIN CLOCK Revision History Rev. Issue Date Description 0.1 04/25/07 Initial Release 0.15 05/03/07 Corrected CLKPWRGD#/PD polarity 0.2 5/18/2007 Updated Test Clarification Table with the correct voltage levels. 0.3 8/31/2007 Updated Input Pin names to indicate maximum Input voltage level 0.4 9/11/2007 Added Logic Level and Input Level Tolerance Columns to Pin Descriptions. ...