mk1573-02 ETC-unknow, mk1573-02 Datasheet

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mk1573-02

Manufacturer Part Number
mk1573-02
Description
Genclock Hsync Video Clock
Manufacturer
ETC-unknow
Datasheet
MDS 1573-02 B
The MK1573 GenClock™ provides genlock
timing for video overlay systems. The device
accepts the horizontal sync (HSYNC) signal as the
input reference clock, and generates a frequency-
locked high speed output. Stored in the device are
the multipliers for 16 combinations of popular
frequencies for analog and digital TV and set-top
box systems. Frequency-locked outputs include
1X, 4X, and 8X the subcarrier frequencies of
NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most
selections, the chip recovers the HSYNC clock by
outputting a low jitter 50% duty cycle version of
HSYNC. Also available is an inverted recovered
HSYNC clock, and a double speed recovered
HSYNC clock.
MicroClock can customize this device for any
other different frequencies.
Description
Block Diagram
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
HSYNC
Input Clock
FS0-3
4
VDD
Buffer
Input
2
GND
2
GenClock
Synthesis
Circuitry
Control
1
Clock
and
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• The -02 version has one frequency changed
• Exact ratios stored in the device eliminate the need
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 4.5V to 5.5V operation
(32MHz was added), and tracks the HSYNC
better than the -01 version.
for external dividers
4X and 8X of those frequencies
OE (all outputs)
HSYNC to Video Clock
Output
Output
Output
Buffer
Buffer
Buffer
Revision 120497
MK1573-02
CLK1
CLK2
CLK3
Printed 11/15/00

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mk1573-02 Summary of contents

Page 1

... Generates 27MHz and 13.5MHz • 2X HSYNC clock available • Recovered HSYNC clock available • Inverted HSYNC clock available • 4.5V to 5.5V operation GND 2 Clock Synthesis and Control Circuitry 1 MK1573-02 HSYNC to Video Clock ™ Output CLK1 Buffer Output CLK2 Buffer Output CLK3 Buffer OE (all outputs) ...

Page 2

... Frequency Select 3. Determines CLK outputs (with given input) per table above. Type Input output power supply connection MDS 1573-02 B Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com GenClock Output Clocks Decoding Table MK1573-02 (MHz) Decode Address HSYNC FS3 FS3:0 (Hex) pin ...

Page 3

... GenClock HSYNC to Video Clock ™ Conditions Minimum Referenced to GND -0.5 0 Max of 10 seconds -65 4.5 2 IOH=-4mA VDD-0.4 IOH=-25mA 2.4 IOL=25mA No Load, VDD=5.0V Each output 0.8 to 2.0V 2.0 to 0.8V At VDD MK1573-02 Typical Maximum Units 7 V VDD+0 °C 250 °C 150 ° ± ...

Page 4

... CLK2 may benefit from a series 33 resistor connected close to the pin (not shown). Video Clock Multipliers/Accuracies In the table on page 2 are the actual multipliers stored in the MK1573-02 ROM, which shows that the accuracies are within one ppm for the output clocks. MDS 1573-02 B Integrated Circuit Systems, Inc. • ...

Page 5

... The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns. MDS 1573-02 B Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com GenClock HSYNC input CLK3 HSYNC input CLK2 CLK3 HSYNC input CLK2 CLK3 5 MK1573-02 HSYNC to Video Clock ™ Revision 120497 Printed 11/15/00 ...

Page 6

... Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com GenClock 45° c Marking MK1573-02S MK1573-02S Comments Original Final version 6 MK1573-02 HSYNC to Video Clock ™ 16 pin SOIC narrow Inches Inches Symbol Min Max A 0.055 0.070 b ...

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