nb7vq14m ON Semiconductor, nb7vq14m Datasheet

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nb7vq14m

Manufacturer Part Number
nb7vq14m
Description
Nb7vq14m 1.8v/2.5v/3.3v 8ghz / 14gbps Differential 1 4 Clock / Data Cml Fanout Buffer W/ Selectable Input
Manufacturer
ON Semiconductor
Datasheet
NB7VQ14M
1.8V/2.5V/3.3V 8GHz /
14Gbps Differential 1:4
Clock / Data CML Fanout
Buffer
Equalizer
Multi−Level Inputs w/ Internal Termination
Description
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the
NB7VQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V
power supply. Therefore, the serial data rate is increased by reducing
Inter−Symbol Interference (ISI) caused by losses in copper
interconnect or long cables. The EQualizer ENable pin (EQEN)
allows the IN/IN inputs to either flow through or bypass the Equalizer
section. Control of the Equalizer function is realized by setting EQEN;
When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When
EQEN is set High, the IN/IN inputs flow through the Equalizer. The
default state at start−up is LOW. As such, NB7VQ14M is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
resistors that are accessed through the VT pin. This feature allows the
NB7VQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The 1:4 fanout design was optimized for low output
skew applications.
performance clock products.
Features
© Semiconductor Components Industries, LLC, 2010
December, 2010 − Rev. 0
The NB7VQ14M is a high performance differential 1:4 CML fanout
The differential inputs incorporate internal 50 W termination
The NB7VQ14M is a member of the GigaComm™ family of high
Input Data Rate > 14 Gb/s, Typical
Input Clock Frequency > 8 GHz, Typical
165 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
< 15 ps Maximum Output Skew
< 0.8 ps Maximum RMS Clock Jitter
< 10 ps pp of Data Dependent Jitter
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Selectable Input Equalization
Operating Range: V
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
Internal Input Termination Resistors, 50 W
w/ Selectable Input
CC
= 1.71 V to 3.6 V with GND = 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional marking information, refer to
CASE 485G
(Note: Microdot may be in either location)
MN SUFFIX
Application Note AND8002/D.
QFN−16
SIMPLIFIED BLOCK DIAGRAM
1
ORDERING INFORMATION
A
L
Y
W
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
EQ
Publication Order Number:
1
16
DIAGRAM*
MARKING
ALYWG
Q14M
NB7V
G
NB7VQ14M/D

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nb7vq14m Summary of contents

Page 1

... Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at start−up is LOW. As such, NB7VQ14M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. ...

Page 2

... Multi−Level Inputs LVPECL, LVDS, CML VREFAC V CC GND EQEN (Equalizer Enable Figure 1. Detailed Block Diagram of NB7VQ14M 0 2:1 MUX EQ 1 http://onsemi.com 2 CML Outputs ...

Page 3

... GND NB7VQ14M VREFAC EQEN Figure 2. QFN−16 Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I LVPECL, CML, LVDS Input VREFAC 4 IN LVPECL, CML, LVDS Input 5 EQEN LVCMOS Input ...

Page 4

Table 3. ATTRIBUTES ESD Protection R − EQEN Input Pulldown Resistor PD Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM ...

Page 5

Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS T = −40°C to 85°C (Note 5) A Symbol Characteristic POWER SUPPLY CURRENT V Power Supply Voltage CC I Power Supply Current (Inputs and Outputs Open) CC CML OUTPUTS (Note 6) V Output HIGH ...

Page 6

Table 6. AC CHARACTERISTICS V Symbol f Maximum Input Clock Frequency; MAX f Maximum Operating Data Rate NRZ, (PRBS23) DATAMAX V Output Voltage Amplitude, EQEN = (Note 15) OUTPP (See Figure 10 Propagation Delay PLH ...

Page 7

Figure 5. Differential Input Driven Single−Ended IHmax V thmax V ILmax thmin V IHmin V ILmin GND ...

Page 8

... Figure 15. Capacitor−Coupled Single−Ended Interface (V Connected REFAC http://onsemi.com NB7VQ14M Open GND Figure 12. LVDS Interface V CC NB7VQ14M REFAC GND Differential Interface Connected REFAC ...

Page 9

... W Driver Q Q Figure 17. Typical NB7VQ14M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1 ORDERING INFORMATION Device NB7VQ14MMNG NB7VQ14MMNHTBG NB7VQ14MMNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

Page 10

... PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1. 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 L1 0.00 0.15 RECOMMENDED 16X 0. 1.84 3.30 0.50 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7VQ14M/D ...

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