nb4l16m ON Semiconductor, nb4l16m Datasheet
nb4l16m
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nb4l16m Summary of contents
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... Driver / Receiver / Buffer/ Translator with Internal Termination Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output. The device is capable of receiving, buffering, and translating a clock or data signal that is as small operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such ideal for SONET, GigE, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23) ...
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... In the differential configuration when the input termination pins (V is applied on D/D input then the device will be susceptible to self-oscillation. NB4L16M NB4L16M Figure 2. Pin Configuration (Top View) I/O Internal 50 W termination pin. See Table 4 (Note 1). ...
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... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. NB4L16M Characteristics R1 R2 ...
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... CML outputs require 50 W receiver termination resistors Input and output parameters vary 1:1 with applied to the complementary input when operating in single-ended mode min varies 1:1 with CMR EE CMRmax input signal. NB4L16M ILD for proper operation. See Figure 14. CC ...
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... CC EE 11. Additive RMS jitter with 50% duty cycle input clock signal. 12. Additive peak-to-peak data dependent jitter with NRZ input data signal, PRBS 2 13. Device-to-device skew is measured between outputs under identical transition @ 0.5 GHz. NB4L16M = 2.375 (Note -40°C ...
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... Figure 3. Output Voltage Amplitude (V vs. Input Clock Frequency (f Temperature at 3.3 V Power Supply 3 -40 25 TEMPERATURE (°C) Figure 5. Rise/Fall Time vs Temperature and Power Supply NB4L16M 450 400 350 -40°C 300 250 200 150 100 50 0 4 Figure 4. Output Voltage Amplitude (V OUTPP ...
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... Input Signal INPP DDJ = 12 ps) Device DDJ = 9 ps TIME (43 ps/div) Figure 11. Typical Output Waveform at 5 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 13 ps) NB4L16M Device DDJ = 2 ps TIME (60 ps/div) Figure 8. Typical Output Waveform at 3.2 Gb/s ^23 with PRBS Device DDJ = 2 ps Figure 10 ...
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... Figure 15. Differential Input Driven Single-Ended thmax IHmax V ILmax IHmin V thmin V ILmin GND Figure 17. V Diagram th NB4L16M V INPP V OUTPP t PHL t PLH Figure 16. Differential Inputs Driven CMmax V CMR V CMmax ...
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... Connect V TD LVDS Connect V TD AC-COUPLED Bias V and V TD RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An External Voltage ( 1.5 V for LVTTL and V THR NB4L16M Figure 19. CML Output Structure CONNECTIONS and and V Together ...
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... All NB4L16M inputs can accept LVPECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from V environment ( ...
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... Figure 23. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION Device NB4L16MMN NB4L16MMNG NB4L16MMNR2 NB4L16MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB4L16M Z Z Figure 22. LVDS to CML Receiver Interface Z No Connect No Connect V REF ...
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... AND FLAG MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 SOLDERING FOOTPRINT* 3.25 0.128 0.30 EXPOSED PAD 0.012 1.50 0.059 0.30 0.012 0.50 0.02 SCALE 10:1 inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB4L16M/D mm ...