74hct163a IK Semicon Co., Ltd, 74hct163a Datasheet
74hct163a
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74hct163a Summary of contents
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... Presettable Counters High-Performance Silicon-Gate CMOS The IN74HCT163A is identical in pinout to the LS/ALS163. The IN74HCT163 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74HCT163A is programmable 4-bit synchronous counter that feature parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls ...
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... CC Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V outputs must be left open. Parameter and GND Pins CC SOIC Package+ Parameter and V should be constrained to the range GND≤(V IN OUT IN74HCT163A Value Unit -0.5 to +7 ± ...
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... V 4 ⎢I ⎢ ≤ 6.0 mA OUT GND 5 GND 5 =0µA OUT V = 2.4 V, Any One Input GND Other Inputs 5.5 I =0µA OUT IN74HCT163A Guaranteed Limit 25 °C ≤85 ≤125 Unit °C °C to -55°C 2.0 2.0 2.0 V 2.0 2.0 2.0 0.8 0.8 0.8 V 0.8 0.8 0.8 4.4 4.4 4.4 V 5.4 5.4 5.4 3.98 3.84 3.7 0.1 0.1 0 ...
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... Typical @25°C f+I V +∆ =5.0 V ± 10%, C =50pF,Input °C to Parameter IN74HCT163A =50pF,Input t =t =6.0 ns Guaranteed Limit ≤85°C ≤125°C Unit 24 20 MHz ...
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... Figure 1. Switching Waveforms Figure 3. Switching Waveforms Figure 5. Switching Waveforms IN74HCT163A Figure 2. Switching Waveforms Figure 4. Switching Waveforms Figure 6. Test Circuit Rev. 00 ...
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... Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. V =Pin 16 CC GND=Pin 8 Figure 7.Expanded logic diagram IN74HCT163A Rev. 00 ...
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... Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram IN74HCT163A Rev. 00 ...
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... TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock f performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter IN74HCT163A guaranteed limits may not apply. Actual max Rev. 00 ...
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... Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. N SUFFIX PLASTIC DIP (MS - 001BB -T- SEATING PLANE SUFFIX SOIC (MS - 012AC SEATING PLANE IN74HCT163A Dimension, mm Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5. 0.36 0.56 F 1.14 1.78 2. 7.62 J 0° 10° ...