at84ad001b ATMEL Corporation, at84ad001b Datasheet
at84ad001b
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at84ad001b Summary of contents
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... Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration) • Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration) -13 • Low Bit Error Rate ( Gsps Application • Instrumentation • Satellite Receivers • Direct RF Down Conversion • WLAN Dual 8-bit 1 Gsps ADC AT84AD001B ™ Smart ADC 2153C–BDC–04/04 1 ...
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... The AT84AD001B is a dual 8-bit 1 Gsps ADC based on advanced high-speed BiCMOS technology. Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω ...
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Figure 1. Simplified Block Diagram CLKI DDRB Vini Vinib Gain control I Calibration Gain/offset ISA I INPUT MUX Gain control Q Calibration Gain/offset ISA Q & FiSDA Vinq Vinqb CLKQ DDRB 2153C–BDC–04/04 Divider Clock Buffer 2 to16 DoirI + 8bit ...
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... Control Functions: Clock and Carrier Recovery... Q AT84AD001B 4 Low Noise Converter (Connected to the Dish) Low Pass Bandpass Bandpass Amplifier Filter Amplifier 11..12 GHz 1..2 GHz Local oscillator I AT84AD001B Q Clock Demodulation Satellite Tuner Tunable IF Band Filter Band Filter AGC Synthesizer 1.5 … 2.5 GHz I Local Oscillator Quadrature 2153C– ...
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Figure 3. Dual Channel Digital Oscilloscope Application Channel B A Channel A A Channel Mode Selection Table 1. Absolute Maximum Ratings Parameter Analog positive supply voltage Digital positive supply voltage Output supply voltage Maximum difference between V and V CCA ...
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... Table 3. Electrical Operating Characteristics in Nominal Conditions Parameter Resolution Power Requirements Positive supply voltage - Analog - Digital Output digital (LVDS) and serial interface Supply current (typical conditions) - Analog - Digital - Output Supply current (1:2 DMUX mode) - Analog - Digital - Output AT84AD001B 6 Symbol Comments V CCA V CCD V CCO INi IniB V ...
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Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Supply current (2 input clocks, 1:2 DMUX mode) - Analog - Digital - Output Supply current (1 channel only, 1:1 DMUX mode) - Analog - Digital - Output Supply current ...
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... Bit Error Rate Gsps Fin = 250 MHz ADC settling time channel (between 10% - 90% of output response 500 mVpp Ini iniB Note: Gain setting is 0 dB, two clock inputs, no standby mode [full power mode], 1:2 DMUX, calibration on. AT84AD001B 8 Symbol 1. 2.25V) V 1125 OS ...
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Table 5. AC Performances Parameter AC Performance Signal-to-noise Ratio Gsps Fin = 20 MHz Gsps Fin = 500 MHz Gsps Fin = 1 GHz Effective Number of Bits ...
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... MHz at F IN1 IN2 Note: One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration phase is necessary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment. AT84AD001B 10 Symbol F int F ...
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Table 7. Switching Performances Parameter Switching Performance and Characteristics - See “Timing Diagrams” on page 12. Maximum operating clock frequency Maximum operating clock frequency in BIT and decimation modes Minimum clock frequency (no transparent mode) Minimum clock frequency (with transparent ...
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... Figure 5. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q Address VIN CLKI or CLKQ DOIA[0:7] or DOQA[0:7] CLKOI or CLKOQ DOIB[0:7] and DOQB[0:7] are high impedance AT84AD001B Pipeline delay = 4 clock cycles Pipeline delay = 3 clock cycles TD2 ...
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Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q Address VIN CLKI DOIA[0:7] DOIB[0:7] DOQA[0:7] DOQB[0:7] CLKOI (= CLKI/2) CLKOI (= CLKI/4) ...
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... Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q Address VIN N CLKI DOIA[0:7] DOQA[0:7] CLKOI DOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impedance AT84AD001B Pipeline delay = 3.5 clock cycles ...
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Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Address VIN N CLKI CLKIN DOQA[0:7] DOQB[0:7] DOIA[0:7] DOIB[0:7] CLKOI (= CLKI/2) CLKOI ...
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... VIN 16 clock cycles CLKI DOIA[0:7] DOQA[0:7] CLKOI DOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impedance Notes: 1. The maximum clock input frequency in decimation mode is 750 Msps. 2. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16. AT84AD001B Pipeline delay = 3.5 clock cycles ...
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Figure 11. Data Ready Reset CLKI or CLKQ DDRB Figure 12. Data Ready Reset 1:1 DMUX Mode TA VIN CLKI or CLKQ DOIA[0:7] or DOQA[0:7] CLKOI or CLKOQ DDRB 1 ns min Note: The Data Ready Reset is taken into ...
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... DMUX Fs/4 mode). The next rising edge of the input clock after reset makes the output clock return to normal mode (after TDR). AT84AD001B ...
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... Differential output data port <D0BQ0:DOBQ7> channel Q <D0BQ0N:DOBQ7N> 2153C–BDC–04/04 VCCA = 3.3V VCCD = 3.3V VCCO = 2.25V VINI VINIB VINQ VINQB AT84AD001B CLKI CLKIB CLKQ CLKQB mode clk data GNDA GNDD GNDO DOIRI, DOIRIN DOIRQ, Differential output IN range DOIRQN data I and Q ...
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... Positive full-scale - 1/2 LSB Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB -248 mV Negative full-scale + 1/2 LSB -250 mV Negative full-scale - 1/2 LSB < -250 mV < Negative full-scale - 1/2 LSB Pin Description Table 10. AT84AD001B LQFP 144 Pin Description Symbol GNDA, GNDD, GNDO V CCA V CCD V CCO V INI V INIB ...
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... Table 10. AT84AD001B LQFP 144 Pin Description (Continued) Symbol CLKQN DDRB DDRBN DOAI0, DOAI1, DOAI2, DOAI3, DOAI4, DOAI5, DOAI6, DOAI7 DOAI0N, DOAI1N, DOAI2N, DOAI3N, DOAI4N, DOAI5N, DOAI6N, DOAI7N, DOBI0, DOBI1, DOBI2, DOBI3, DOBI4, DOBI5, DOBI6, DOBI7 DOBI0N, DOBI1N, DOBI2N, DOBI3N, DOBI4N, DOBI5N, DOBI6N, DOBI7N ...
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... Table 10. AT84AD001B LQFP 144 Pin Description (Continued) Symbol CLKOIN CLKOQ CLKOQN VtestQ, VtestI Cal Vdiode Figure 14. AT84AD001B Pinout (Top View) AT84AD001B 22 Pin number 122 132 131 52 LQFP 144 1.4 mm Atmel - Dual 8-bit Function Inverted phase (-) output clock channel I ...
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Typical Characterization Results Typical Full Power Input Bandwidth 2153C–BDC–04/04 Nominal conditions (unless otherwise specified): • 3.3V 3.3V; V CCA CCD CCO • 500 mVpp full-scale differential input INI ...
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... Typical Crosstalk Typical DC, INL and DNL Patterns AT84AD001B 24 Figure 16. Crosstalk (Fs = 500 Msps 100 200 300 Note: Measured on the AT84AD001TD-EB Evaluation Board. 1:2 DMUX mode, Fs/4 DR type Figure 17. Typical INL ( Msps, Fin = 1 MHz, Saturated Input) 0,6 0,4 0,2 0 -0,2 -0,4 -0 ...
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Typical Step Response 2153C–BDC–04/04 Figure 18. Typical DNL ( Msps, Fin = 1 MHz, Saturated Input) 0,3 0,2 0,1 0 -0,1 -0,2 -0 Figure 19. Step Response 250 200 150 100 50 0 ...
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... AT84AD001B 26 Figure 20. Step Response (Zoom) 250 200 150 100 50 0 4.9E-09 • Gsps • Pclock = 0 dBm • Fin = 500 MHz • Pin = -1 dBFS Figure 21. Step Response 250 200 150 100 50 0 4.9E-13 2.5E-10 5.0E-10 7.5E-10 1.0E-09 1.3E-09 1.5E-09 1.8E-09 90 160 ps 10% 6.1E-09 7.4E-09 Time (s) Channel IA Channel QA Time (s) Channel IA Channel QA 2153C–BDC–04/04 ...
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Typical Dynamic Performances Versus Sampling Frequency 2153C–BDC–04/04 Figure 22. Step Response (Zoom) 250 200 150 100 50 0 9.8E-10 Figure 23. ENOB Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 ...
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... Typical Dynamic Performances Versus Input Frequency AT84AD001B 28 Figure 25. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) -48 -50 -52 -54 -56 -58 -60 100 300 Figure 26. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/ 100 300 Figure 27. ENOB Versus Input Frequency ( Gsps) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 0 200 ...
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Figure 28. SFDR Versus Input Frequency ( Gsps) -35 -40 -45 -50 -55 -60 -65 0 200 Figure 29. THD Versus Input Frequency ( Gsps) -35 -40 -45 -50 -55 -60 -65 0 200 Figure ...
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... Figure 33 Gsps and Fin = 1 GHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps) 250 200 150 100 513 1025 1537 2049 Samples Note: The spectra are given with respect to the output clock frequency observed by the acquisition system (Figures 31 to 33). AT84AD001B -20 -40 -60 - -100 Ch QA -120 0 2561 3073 ...
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Figure 34 Gsps and Fin = 20 MHz (Interleaving Mode Fint = 2 Gsps, Fs/4 DR Type, FiSDA = -15 ps, ISA = -50 ps) 250 200 150 100 2048 4095 6142 Samples Figure ...
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... Typical Performance Sensitivity Versus Power Supplies and Temperature AT84AD001B 32 Figure 36. ENOB Versus CCA Fs/4 DR Type, ISA = -50 ps) 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 3.1 3.15 3.2 Figure 37. SFDR Versus CCA Fs/4 DR Type, ISA = -50 ps) -40 -45 -50 -55 -60 3.1 3.15 3.2 ( Gsps, Fin = 500 MHz, 1:2 DMUX, CCD 3.25 3.3 3.35 3.4 3.45 Vcca = Vccd (V) ( Gsps, Fin = 500 MHz, 1:2 DMUX, CCD 3 ...
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Figure 38. THD Versus CCA Fs/4 DR Type, ISA = -50 ps) -40 -45 -50 -55 -60 3.1 3.15 3.2 Figure 39. SNR Versus CCA Fs/4 DR Type, ISA = -50 ps) 45.0 ...
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... AT84AD001B 34 Figure 40. ENOB Versus Junction Temperature ( Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 -50 -25 0 Figure 41. SFDR Versus Junction Temperature ( Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -35 -40 -45 -50 -55 -60 -65 -50 - Gsps 20 MHz 1 Gsps 502 MHz 1 Gsps 998 MHz 100 Tj (˚C) 1 Gsps 998 MHz ...
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Figure 42. THD Versus Junction Temperature ( Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -35 -40 -45 -50 -55 -60 -50 -25 0 Figure 43. SNR Versus Junction Temperature ( Gsps, 1:2 ...
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... Test and Control Features 3-wire Serial Interface Control Setting Table 11. 3-wire Serial Interface Control Settings Mode Mode = 1 (2.25V) Mode = 0 (0V) AT84AD001B 36 Characteristics 3-wire serial bus interface activated 3-wire serial bus interface deactivated Nominal setting: Dual channel I and Q activated One clock gain DMUX mode 1:1 DRDA I & ...
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Serial Interface and Data Description Table 12. 3-wire Serial Interface Address Setting Description Address Setting Standby Gray/binary mode 1:1 or 1:2 DMUX mode Analog input MUX 000 Clock selection Auto-calibration Decimation test mode Data Ready Delay Adjust Analog gain ...
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... In the Gray mode, when the input signal is overflow (that is, the differential analog input is greater than 250 mV), the output data must be corrected using the output DOIR: If DOIR = 1: Data7 unchanged Data6 = 0, Data5 = 0, Data4 = 0, Data3 = 0, Data2 = 0, Data1 = 0, Data0 = 0. In 1:2 DMUX mode, only one out-of-range bit is provided for both A and B ports. AT84AD001B 38 OFF: Data4 = 0 BIT Inactive Data0 = 1 ...
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Table 13. 3-wire Serial Interface Data Setting Description Setting for Address: 000 D15 D14 Full standby mode X (2) Standby channel I X (3) Standby channel standby mode X Binary output mode X Gray output mode X ...
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... For clock rates > 250 Msps and < 500 Msps use and For clock rates > 125 Msps and < 250 Msps use and For low clock rates < 125 Msps use and 3-wire Serial Interface Timing Description AT84AD001B 40 (1) D13 D12 ...
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Figure 44. Write Chronogram Mode sclk sldn sdata Internal register Reset setting value Reset 2153C–BDC–04/04 • A minimum of one clock cycle with “sldn” returned requested to close the write procedure and make the interface ready for ...
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... Calibration Description AT84AD001B 42 The AT84AD001B offers the possibility of reducing offset and gain matching between the two ADC cores. An internal digital calibration may start right after the 3-wire serial interface has been loaded (using data D12 of the 3-wire serial interface with address 000) ...
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... Built-In Test (BIT) 2153C–BDC–04/04 The calibration phase is necessary when using the AT84AD001B in interlace mode, where one analog input is sampled at both ADC cores on the common input clock’s ris- ing and falling edges. This operation is equivalent to converting the analog signal at twice the clock frequency During the ADC’ ...
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... D15 D14 D13 D12 D11 Decimation Mode Die Junction Temperature Monitoring Function AT84AD001B 44 Example: Address = 110 Data = D10 One should then obtain 01010101 on Port B and 10101010 on Port A. When the dynamic mode is chosen (Data1 = 1) port B outputs a rising ramp while Port A outputs a decreasing one ...
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VtestI, VtestQ Equivalent Input/Output Schematics 2153C–BDC–04/04 The VBE diode’s forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure 48. Figure 48. Diode Characteristics Versus T 860 840 820 800 780 760 740 720 700 ...
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... Figure 51. Analog Input Model DC Coupling (Common Mode = Ground = 0V) Vinl Reverse 50Ω Termination GND VinI VinI Double Pad VinQ Reverse 50Ω Termination GND VinQ AT84AD001B 46 Figure 50. Simplified Data Ready Reset Buffer Model DDRB VCCD/2 DDRBN Vcca ESD GND – 0.4V ESD MAX GND VinQ Double ...
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Definitions of Terms Table 16. Definitions of Terms Abbreviation Definition BER Bit Error Rate Differential DNL Non-Linearity Effective Number of ENOB Bits Full Power Input FPBW Bandwidth Inter-Modulation IMD Distortion Integral INL Non-Linearity Aperture JITTER uncertainty NPR Noise Power Ratio ...
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... THD Distortion TPD Pipeline Delay TR Rise Time AT84AD001B 48 Description The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale The ratio of input offset variation to a change in power supply voltage The ratio expressed the RMS signal amplitude, set below full-scale, to the RMS value of the highest spectral component (peak spurious spectral component) ...
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Table 16. Definitions of Terms (Continued) Abbreviation Definition TRDR Data Ready Reset Delay TS Settling Time VSWR Voltage Standing Wave Ratio 2153C–BDC–04/04 Description The delay between the falling edge of the Data Ready output asynchronous reset signal (DDRB) and the ...
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... Using the AT84AD001B Dual 8-bit 1 Gsps ADC Decoupling, Bypassing and Grounding of Power Supplies Figure 53. V and V Bypassing and Grounding Scheme CCD CCA PC Board 3.3V 1µF PC Board GND Figure 54. V Bypassing and Grounding Scheme CCO PC Board 2.25V 1µF PC Board GND Note: L and C values must be chosen in accordance with the operation frequency of the application. ...
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Analog Input Implementation Figure 56. Termination Method for the ADC Analog Inputs in DC Coupling Mode Channel I Channel Q 2153C–BDC–04/04 The analog inputs of the dual ADC have been designed with a double pad implementa- tion as illustrated in ...
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... Figure 57. Termination Method for the ADC Analog Inputs in AC Coupling Mode 50Ω Source Channel I 50Ω Source Channel Q Clock Implementation AT84AD001B 52 50Ω GND GND 50Ω 50Ω GND GND 50Ω The ADC features two different clocks ( that must be implemented as shown in Figure 58 ...
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Figure 59. Single-ended Termination Method for Clock I or Clock Q AC coupling capacitor 50Ω Source AC coupling capacitor 50Ω Output Termination in 1:1 Ratio 2153C–BDC–04/04 CLK CLKB When using the integrated DMUX in 1:1 ratio, the valid port is ...
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... Note: If the outputs are to be used in single-ended mode recommended that the true and false signals be terminated with a 50Ω resistor. Using the Dual ADC With and ASIC/FPGA Load AT84AD001B 54 Floating (High Z) Dual ADC Package VCCO Figure 61 on page 55 illustrates the configuration of the dual ADC (1:2 DMUX mode, independent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential addi- tional DMUXes used to halve the speed of the dual ADC outputs ...
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Figure 61. Dual ADC and ASIC/FPGA Load Block Diagram CLKI/CLKIN @ FsI CLKQ/CLKQN @ FsQ Note: The demultiplexers may be internal to the ASIC/FPGA system. 2153C–BDC–04/04 Data rate = FsI/2 Port A DEMUX 8 :16 Channel I Data rate = ...
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... Thermal Resistance from Junction to Top of Case Thermal Resistance from Junction to Bottom of Case Thermal Resistance from Junction to Bottom of Air Gap AT84AD001B 56 The following model has been extracted from the ANSYS FEM simulations. Assumptions: no air, no convection and no board. Silicon Junction 0.6˚C/watt λ = 0.007W/cm/˚C 1.4˚ ...
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Thermal Resistance from Junction to Ambient Thermal Resistance from Junction to Board 2153C–BDC–04/04 The thermal resistance from the junction to ambient is 25.2° C/W typical. Note: In order to keep the ambient temperature of the die within the specified limits ...
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... Ordering Information Part Number Package AT84XAD001BTD LQFP 144 AT84AD001BCTD LQFP 144 AT84AD001BITD LQFP 144 AT84AD001TD-EB LQFP 144 AT84AD001B 58 Temperature Range Screening Ambient Prototype C grade Standard 0°C < T < 70° grade Standard -40°C < T < 85°C A Ambient Prototype Comments Prototype version ...
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Packaging Information Figure 63. Type of Package 0.20 RAD max. A 0.25 C 0.17 max Note: Thermally enhanced package: LQFP 144 1.4 mm. 2153C–BDC–04/04 Dims ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...