sx8654evk Semtech Corporation, sx8654evk Datasheet - Page 42

• Manufacturer Part Number: sx8654evk
• Description: Haptics Enabled 4/5-wire Resistive Touchscreen Controller With Proximity Sensing
• Manufacturer: Semtech Corporation

ADVANCED COMMUNICATIONS & SENSING
11 I2C I
11.1 Introduction
The chip is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated
January, 2000. The chip has a few user-accessible internal 8-bits registers to set the various parameters of
operation (Cf. § 12 for detailed configuration registers description). The I2C interface has been designed for
program flexibility, in that once the slave address has been sent to the chip enabling it to be a slave
transmitter/receiver, any register can be written or read independently of each other. The start and stop
commands frame the data-packet and the repeat start condition is allowed if necessary.
2 lines are used to exchange data between an external master host and the slave device:
Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by
the chip. The chip is not CBUS compatible and can operate in standard mode (100kbit/s) or fast mode
(400kbit/s).
11.2 I2C Address
On the QFN package an ADDR pin is made available to select between the two pre-programmed I2C addresses
of the device. On the CSP package ADDR is internally connected to ground.
This is illustrated in table below.
Please note that upon request, a custom I2C Address can be pre-programmed by Semtech.
11.3 Write Register
The I2C write register sequence is given in figure below. After the start condition [S], the chip slave address
(SA) is sent, followed by an eighth bit (W=‘0’) indicating a write. The chip then acknowledges [A] that it is being
addressed, and the host sends a CR byte consisting in ‘00’ followed by the chip register address (RA). The chip
acknowledges [A] and the host sends the appropriate data byte (WD0) to be written.
acknowledges [A]. In case the host needs to write more data, a succeeding data byte will follow (WD1),
acknowledged by the slave [A]. This sequence will be repeated until the host terminates the transfer with the
stop condition [P].
The register address increments automatically when successive data bytes (WD1...WDn) are supplied by the
host.
Rev 1 – 25
SCL : Serial CLock
SDA : Serial DAta
NTERFACE
th
Package
July 2011
QFN
CSP
ADDR
0
1
0
Figure 50 – I2C Write Register
0x48 (1001000)
0x49 (1001001)
0x48 (1001000)
Table 8 – I2C Address
Address
Resistive Touchscreen Controller with Proximity Sensing
42
Description
First I2C address
Second I2C address
First (and unique) I2C address
SX8657/SX8658
Haptics Enabled 4/5-Wire
www.semtech.com
Again the chip