sx8634 Semtech Corporation, sx8634 Datasheet - Page 62

• Manufacturer Part Number: sx8634
• Description: Low Power, Capacitive Button And Slider Touch Controller 12 Sensors With Enhanced Led Drivers And Proximity Sensing
• Manufacturer: Semtech Corporation

SX8634
Low Power, Capacitive Button and Slider Touch Controller
(12 sensors) with Enhanced LED Drivers and Proximity Sensing
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
6 I2C I
NTERFACE
The I2C implemented on the SX8634 is compliant with:
- standard (100kb/s), fast mode (400kb/s)
- slave mode
- 7 bit address (default 0x2B). The default address can be changed in the NVM at address 0x04.
The host can use the I2C to read and write data at any time. The effective changes will be applied at the next
processing phase (section 3.3).
Three types of registers are considered:
- status (read). These registers give information about the status of the capacitive buttons, slider, GPIs, operation
modes etc…
- control (read/write). These registers control the soft reset, operating modes, GPIOs and offset compensation.
- SPM gateway (read/write). These registers are used for the communication between host and the SPM. The
SPM gateway communication is done typically at power up and is not supposed to be changed when the
application is running. The SPM needs to be re-stored each time the SX8634 is powered down.
The SPM can be stored permanently in the NVM memory of the SX8634. The SPM gateway communication over
the I2C at power up is then not required.
The I2C will be able to read and write from a start address and then perform read or writes sequentially, and the
address increments automatically.
The supported I2C access formats are described in the next sections.
6.1 I2C Write
The format of the I2C write is given in Figure 52.
After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The
SX8634 then Acknowledges [A] that it is being addressed, and the Master sends an 8 bit Data Byte consisting of
the SX8634 Register Address (RA). The Slave Acknowledges [A] and the master sends the appropriate 8 bit Data
Byte (WD0). Again the Slave Acknowledges [A]. In case the master needs to write more data, a succeeding 8 bit
Data Byte will follow (WD1), acknowledged by the slave [A]. This sequence will be repeated until the master
terminates the transfer with the Stop condition [P].
I2C write
Figure 52
The register address is incremented automatically when successive register data (WD1...WDn) is supplied by the
master.
Revision 7_6, October 10
© 2010 Semtech Corp.
www.semtech.com
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