tsc21020f ATMEL Corporation, tsc21020f Datasheet
tsc21020f
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tsc21020f Summary of contents
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... Notes: 1. Design using patent from INPG-CNRS Denis BESSOT/Raoul VELAZCO 2. Product licensed from Analog Devices Inc Error/Device/Day (worst case) Rad. Hard 32/40-bit IEEE Floating Point DSP TSC21020F Rev. 4153I-AERO–04/07 1 ...
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... Functional Block Diagram TSC21020F 2 4153H–AERO–04/07 ...
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... This allows full-speed execution of core, looped operations such as digital filter multiply- accumulates and FFT butterfly processing. The TSC21020F provides hardware to implement circular buffers in memory, which are common in digital filters and Fourier transform implementations. It handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplify- ing implementation ...
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... ADSP- 21020 EZ-ICE Emulator TSC21020F 4 The TSC21020F is supported with a complete set of software and hardware develop- ment tools from Analog Devices. The ADSP-21000 Family Development System from Analog Devices includes development software, an evaluation board and an in-circuit emulator. Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx assembly source code ...
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... EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc. This data sheet provides a general overview of TSC21020F functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP- 21020 User's Manual. For development system and programming reference informa- tion, refer to the ADSP-21000 Family Development Software Manuals and the ADSP- 21020 Programmer's Quick Reference ...
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... Architecture Overview Computation Units Data Register File TSC21020F 6 Figure 1 shows a block diagram of the TSC21020F. The processor features: • Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register File • Two Data Address Generators (DAG 1, DAG 2) • Program Sequencer with Instruction Cache • ...
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... With a large number of buses connecting the registers to the computation units, data flow between computation units and from/to off-chip memory is unconstrained and free from bottlenecks. The 10-port register file and Harvard architecture of the TSC21020F allow the following nine data transfers to be performed every cycle: • ...
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... An interrupt can occur at any time while the TSC21020F is executing a program. Inter- nal events that generate interrupts include arithmetic exceptions, which allow for fast trap handling and recovery. ...
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... Figure 2. Basic System Configuration External devices can gain control of the processor's memory buses from the TSC21020F by means of the bus request/grant signals (BR and BG). To grant its buses in response to a bus request, the TSC21020F halts internal operations and places its 9 ...
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... PMTS) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the TSC21020F unless it requires a memory access from the affected interface. The three-state controls make it easy for an external cache controller to hold the TSC21020F off the bus while it updates an external cache memory ...
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... Pin Descriptions 4153H–AERO–04/07 This section describes the pins of the TSC21020F. When groups of pins are identified with subscripts, e.g. PMD , the highest numbered pin is the MSB (in this case, 47-0 PMD ). Inputs identified as synchronous (S) must meet timing requirements with 47 respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN ...
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... External clock input to the TSC21020F. The instruction cycle rate is CLKIN I equal to CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. Sets the TSC21020F to a known state and begins execution at the RESET I/A program memory location specified by the hardware reset vector (address). This input must be asserted (low) at power-up. ...
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... Test Reset. Resets the test state machine. TRST must be asserted TRST I/A (pulsed low) after power-up or held low for proper operation of the TSC21020F. TRST has a 20 kΩ internal pull-up resistor. No Connect. No Connects are reserved pins that must be left open and NC unconnected. Table 1. PGA Pin Configuration ...
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... TSC21020F 14 Table 1. PGA Pin Configuration (Continued) PGA Pin PGA Pin Location Name Location Name A16 DMA22 S12 DMTS D13 DMA23 T12 DMACK C14 DMA24 L17 PMA0 B15 DMA25 M18 PMA1 B14 DMA26 M15 PMA2 D12 DMA27 M16 PMA3 C13 DMA28 M17 ...
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Table 2. MQFP Pin Configuration MQFP_F Pin MQFP_F Location Name Location 1 IGND 65 2 IVDD 66 3 DMD19 67 4 DMD18 68 5 DMD17 69 6 DMD16 70 7 EGND 71 8 DMD15 72 9 DMD14 73 10 ...
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... Multifunction instructions enable simultaneous multiplier and ALU operations, as well as computations executed in parallel with data transfers. The addressing power of the TSC21020F gives flexibility in moving data both internally and externally. The TSC21020F assembly language uses an algebraic syntax for ease of coding and readability. MQFP_F ...
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... For example, the ALU supports 21 fixed-point operations and 24 floating- point operations; each of these operations can be the compute portion of an instruction. The following pages provide an overview and summary of the TSC21020F instruction set. For complete information, see the ADSP-21020 User's Manual from Analog Devices ...
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... Compute and Move or Modify Instructions TSC21020F 18 1. compute condition compute ; 3a. IF condition compute, 3b. IF condition compute, 3c. IF condition compute, 3d. IF condition compute, 4a. IF condition compute, 4b. IF condition compute, 4c. IF condition compute, dreg = 4d. IF condition compute, dreg = 5. IF condition compute, ureg1 = ureg2; ...
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PM < addr24 > | 14b. ureg = DM < addr32 > < addr24 > 15a. DM (< data32 >, Ia) = ureg ; | | PM (< data24 >, Ic) | 15b. ...
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... TSC21020F 20 Table 3. Syntax Notation Conventions Notation Meaning ureg Universal register (from Table 3) sreg System register (from Table 3) dreg R15-R0, F15-F0; register file location Ia I7-I0; DAG1 index register Mb M7-M0; DAG1 modify register Ic I15-I8; DAG2 index register Md M15-M8; DAG2 modify register 4153H–AERO–04/07 ...
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Table 4. Condition and Termination Codes Name Description eq ALU equal to zero ne ALU not equal to zero ge ALU greater than or equal to zero lt ALU less than zero le ALU less than or equal to ...
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... TSC21020F 22 Table 5. Universal Registers Name Function Register file R15-R0 Register file locations Program Sequencer (1) PC Program counter; address of instruction currently executing PCSTK Top of PC stack PCSTKP PC stack pointer (1) FADDR Fetch address (1) DADDR Decode address LADDR Loop termination address, code; top of loop address stack CURLCNTR Current loop counter ...
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Table 5. Universal Registers (Continued) Name Function DMBANK3 Data memory bank 3 upper boundary (1) DMADR Copy of last data memory address PMWAIT Wait state and page size control for program memory PMBANK1 Program memory bank 1 upper boundary ...
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... TSC21020F 24 Table 6. ALU Compute Operations (Continued) Fixed-Point Rn = CLIP AND XOR NOT Rx Note: Rn, Rx, Ry R15-R0; register file location, fixed-point Fn, Fx, Fy F15-F0; register file location, floating point Floating-Point Fn = CLIP ...
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Multiplier Compute Operations 4153H–AERO–04/ Ry MRF MRB MRF = MR F MRB ...
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... TSC21020F 26 Table 7. Shifter and Shifter Immediate Compute Operations Shifter Rn = LSHIFT LSHIFT ASHIFT ASHIFT ROT BCLR BSET BTGL BTST FDEP FDEP ...
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Table 9. Multifunction Compute Operations Floating-Point ( F3-0 F7- F11-8 + F15-12 ( F3-0 F7- F11-8 - F15-12 ( F3-0 F7- FLOAT R11-8 by R15-12 (1) Fm ...
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... TSC21020F 28 Table 10. Interrupt Vector Addresses and Priorities (Continued) No Vector Address (Hex) Function 13 0x68 14 0x70 15 0x78 16 0x80 17 0x88 18 0x90 19-23 0x98-0xB8 24-31 0xC0-OxF8 Note: 1. Nonmaskable Reserved Timer = 0 (low priority option) Fixed-point overflow Floating-point overflow Floating-point underflow Floating-point invalid operation Reserved User software interrupts 4153H–AERO–04/07 ...
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... AMB The TSC21020F features proprietary input protection circuitry to dissipate high-energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the TSC21020F has been classified as a Class 2 devices, with the ability to withstand up to 2000V ESD. Prosper ESD precautions are strongly recommended to avoid functional damage or per- formance degradation ...
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... DMPAGE, FLAG3-0, TDO. 7. Applies to IVDD pins supply current for total supply current. 8. Applies to IVDD pins. Idle refers to TSC21020F state of operation during execution of the IDLE instruction. 9. Guaranteed but not tested. 10. Applies to all signal pins. 11. Although specified for TTL outputs, all TSC21020F outputs are CMOS-compatible and will drive loads ...
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... V and CLKIN (not including clock oscillator start-up time Specification only applies in cases where multiple TSC21020F processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User's Manual from Analog Devices for reset sequence information. ...
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... Interrupts Timer TSC21020F 32 Figure 4. Reset Parameter t IRQ3-0 Setup before CLKIN High SIR t IRQ3-0 Hold after CLKIN High HIR t IRQ3-0 Pulse Width IPW Note Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met ...
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Flags Figure 7. Flags 4153H–AERO–04/07 Parameter (2) t FLAG3-0 Setup before CLKIN SFI IN High (2) t FLAG3-0 Hold after CLKIN High HFI IN (2) t FLAG3-0 Delay from xRD, DWRFI IN xWR Low (2) t FLAG3-0 Hold after xRD, ...
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... Bus Request/Bus Grant Figure 8. Bus Request/Bus Grant TSC21020F 34 Parameter Min t BR Hold after CLKIN High HBR t BR Setup before CLKIN High SBR t Memory Interface Disable DMDBGL ( Low t CLKIN High to Memory DME Interface Enable t CLKIN High to BG Low DBGL t CLKIN High to BG High ...
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External Memory Three-State Control Figure 9. External Memory Three-State Control 4153H–AERO–04/07 Parameter Min t XTS, Setup before CLKIN 14 STS High t XTS Delay after DADTS Address, Select t XTS, Delay after XRD, DSTS XWR Low t Memory Interface 0 ...
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... Memory Read TSC21020F 36 Parameter t Address, Select to Data Valid DAD t xRD Low to Data Valid DRLD t Data Hold from Address, HDA Select t Data Hold from xRD High HDRH t xACK Delay from Address DAAK t xACK Delay from xRD Low DRAK t xACK Setup before CLKIN ...
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Figure 10. Memory Read Memory Write 4153H–AERO–04/07 Parameter Min t xACK Delay from DAAK Address, Select t xACK Delay from xWR DWAK Low t xACK Setup before CLKIN 14 SAK High t xACK Hold after CLKIN 0 HAK High t ...
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... Figure 11. Memory Write TSC21020F 38 Parameter Min t Address, Select Hold 1 DWHA (2) after xWR Deasserted t Data Hold after xWR 0 HDWH (2) Deasserted t xPAGE Delay from DAP Address, Select t CLKIN High to xWR 16 DCKWL Low t xWR High to xWR or xRD 17 WWR Low t Data Disable before 13 DDWR xWR or xRD Low ...
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IEEE 1149.1 Test Access Port Figure 12. IEEE 1149.1 Test Access Port 4153H–AERO–04/07 Parameter t TCK Period TCK t TDI, TMS Setup before TCK STAP High t TDI, TMS Hold after TCK High HTAP t System Inputs Setup before SSYS ...
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... Figure 13. Output Enable/Disable Test Conditions Output Disable Time Output Enable Time TSC21020F 40 Output pins are considered to be disable when they stop driving, go into a high-imped- ance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, C current, I ...
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... Figure 14. Equivalent Device Loading for AC Measurements (Includes all Fixtures) To determine the data output hold time in a particular system, first calculate t the above equation. Choose ∆ the difference between the TSC21020F's output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be ...
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... TSC21020F 42 Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature 1 Note: (1) OUTPUT DMD39–0, FLAG3–0 Figure 17. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature Note: (1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3– ...
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Power Dissipation 4153H–AERO–04/07 Figure 18. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature –1.7 – Note: (1) OUTPUT PINS BG, TIMEXP, FLAG3–0, PMD47–0, DMD39–0 Figure 19. Typical ...
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... The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1 µF ceramic). Keep each capacitor's lead and trace length to the pins as short as possible. This low inductive path provides the TSC21020F with the peak currents required when its output drivers switch. The capacitors' ground leads should also be short and connect directly to the ground plane ...
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... IVDD and EVDD traces is also recommended. The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG test access port of the TSC21020F to monitor and control the target board processor during emulation. The EZ-ICE probe requires that CLKIN, TMS, TCK, TRST, TDI, TDO, and GND be made accessible on the target system via a 12-pin connector (pin strip header) such as that shown in Figure 20 ...
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... BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST on the connector) or held low for proper operation of the TSC21020F. 4153H–AERO–04/07 ...
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... Ordering Information Part Number Temperature Range TSC21020F-20MA-E TSC21020F-20MB-E 5962-9953901QXC -55 to +125°C 5962-9953901VXC -55 to +125°C 951200201 -55 to +125°C TSC21020F-20MC-E TSC21020F-20MC-SV -55 to +125°C Package Drawings 223-pin Ceramic Pin Grid Array 4153H–AERO–04/07 Speed 25°C 20 MHz 25°C 20 MHz 20 MHz 20 MHz 20 MHz 25° ...
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... MQFP-F Package TSC21020F 48 C 2.54 BSC D 46.74 E 46.74 H 0.41 L 3.05 Q 1.14 Top View Symbol Min. A 0.095 C 0.004 D 2.095 D 1.450 1 E 2.095 E 1.450 1 e 0.020 BSC f 0.006 A 0.081 1 A 0.002 2 L 0.323 N 1 .100 BSC 47.75 1.840 47.75 1.840 0.51 0.16 3.56 .120 1.40 0.45 Mils Max Min. 0.125 2.41 0.008 0.10 2.195 53.23 1.470 36 ...
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... Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for useas components in applications intended to support or sustainlife. ©2007 Atmel Corporation. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...