atf16v8c ATMEL Corporation, atf16v8c Datasheet - Page 6

• Manufacturer Part Number: atf16v8c
• Description: High- Performance Ee Pld
• Manufacturer: ATMEL Corporation

Power-down Mode
The ATF16V8C includes an optional pin controlled power-
down feature. Device pin 4 may be configured as the
power-down pin. When this feature is enabled and the
power-down pin is high, total current consumption drops to
less than 100 µA. In the power-down mode, all output data
and internal logic states are latched and held. All registered
and combinatorial output data remains valid. Any outputs
which were in a HI-Z state at the onset of power-down will
remain at HI-Z. During power-down, all input signals except
the power-down pin are blocked. The input and I/O pin
keeper circuits remain active to insure that pins do not float
to indeterminate levels. This helps to further reduce system
power.
Selection of the power-down option is specified in the
ATF16V8C logic design file. The logic compiler will include
this option selection in the otherwise standard 16V8
JEDEC fuse file. When the power-down feature is not spec-
ified in the design file, pin 4 is available as a logic input, and
there is no power-down pin. This allows the ATF16V8C to
be programmed using any existing standard 16V8 fuse file.
Note:
Registered Output Preload
The ATF16V8C’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by approved
programmers.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF16V8C fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse will be programmed last, as its effect is
immediate.
Input and I/O Pin Keeper Circuits
The ATF16V8C contains internal input and I/O pin keeper
circuits. These circuits allow each ATF16V8C pin to hold its
previous value even when it is not being driven by an
6
Some programmers list the JEDEC-compatible 16V8C
(No PD used) separately from the non-JEDEC compati-
ble 16V8CEXT. (EXT for extended features.)
ATF16V8C
external source or by the device’s output buffer. This helps
insure that all logic array inputs are at known, valid logic
levels. This reduces system power by preventing pins from
floating to indeterminate levels. By using pin keeper circuits
rather than pull-up resistors, there is no DC current
required to hold the pins in either logic state (high or low).
These pin keeper circuits are implemented as weak feed-
back inverters, as shown in the Input Diagram below.
These keeper circuits can easily be overdriven by standard
TTL- or CMOS-compatible drivers. The typical overdrive
current required is 40 µA.
Input Diagram
I/O Diagram