atf22lv10cqz ATMEL Corporation, atf22lv10cqz Datasheet - Page 6

• Manufacturer Part Number: atf22lv10cqz
• Description: High- Performance Ee Pld
• Manufacturer: ATMEL Corporation

4.4
4.4.1
4.4.2
4.5
4.6
4.7
6
Input Test Waveforms
Pin Capacitance
Power-up Reset
Preload of Register Outputs
ATF22LV10C(Q)Z
Input Test Waveforms and Measurement Levels
Output Test Loads
Note:
Table 4-1.
Note:
The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point
delayed slightly from V
state will depend on the polarity of the buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
required:
The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register
with either a high or a low. This feature will simplify testing since any state can be forced into the
registers to control test sequencing. A JEDEC file with preload is generated when a source file
C
C
1. The V
2. The clock must remain stable during T
3. After T
IN
I/O
high.
Similar competitors devices are specified with slightly different loads. These load differences may
affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet
compatible device specification conditions.
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
CC
PR
Pin Capacitance (f = 1 MHz, T = 25°C
rise must be monotonic and start below 0.7V.
, all input and feedback setup times must be met before driving the clock pin
Typ
5
6
CC
crossing V
Max
8
8
CC
RST
actually rises in the system, the following conditions are
, all registers will be reset to the low state. The output
PR
.
Units
(1)
pF
pF
)
Conditions
V
V
OUT
IN
= 0V
= 0V
0779L–PLD–12/05