at94k05al-25aqi ATMEL Corporation, at94k05al-25aqi Datasheet - Page 64

• Manufacturer Part Number: at94k05al-25aqi
• Description: 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

64
AT94K Series FPSLIC
External Interrupt Mask/Flag Register – EIMF
• Bits 3..0 - INT3, 2, 1, 0: External Interrupt Request 3, 2, 1, 0 Enable
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the corresponding external pin interrupt is enabled. The external interrupts are always nega-
tive edge triggered interrupts, see “Sleep Modes” on page 66.
• Bits 7..4 - INTF3, 2, 1, 0: External Interrupt 3, 2, 1, 0 Flags
When a falling edge is detected on the INT3, 2, 1, 0 pins, an interrupt request is triggered. The
corresponding interrupt flag, INTF3, 2, 1, 0 becomes set (one). If the I-bit in SREG and the
corresponding interrupt enable bit, INT3, 2, 1, 0 in EIMF, are set (one), the MCU will jump to
the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag is cleared by writing a logic 1 to it.
Timer/Counter Interrupt Mask Register – TIMSK
• Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 6 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is exe-
cuted if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 5 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is exe-
cuted if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 4 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter inter-
rupt flag register – TIFR.
• Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 input capture event interrupt is enabled. The corresponding interrupt is exe-
cuted if a capture-triggering event occurs on pin 29, (IC1), i.e., when the ICF1 bit is set in the
Timer/Counter interrupt flag register – TIFR.
Bit
$3B ($5B)
Read/Write
Initial Value
Bit
$39 ($39)
Read/Write
Initial Value
7
INTF3
R/W
0
7
TOIE1
R/W
0
6
INTF2
R/W
0
6
OCIE1A
R/W
0
5
INTF1
R/W
0
5
OCIE1B
R/W
0
4
INTF0
R/W
0
4
TOIE2
R/W
0
3
INT3
R/W
0
3
TICIE1
R/W
0
2
INT2
R/W
0
2
OCIE2
R/W
0
1
INT1
R/W
0
1
TOIE0
R/W
0
Rev. 1138F–FPSLI–06/02
0
INT0
R/W
0
0
OCIE0
R/W
0
EIMF
TIMSK