mc33157dw ON Semiconductor, mc33157dw Datasheet - Page 4

• Manufacturer Part Number: mc33157dw
• Description: Half Bridge Controller And Driver For Industrial Linear Tubes
• Manufacturer: ON Semiconductor

Pin
10
1
2
3
4
5
6
7
8
9
C SWEEP
Symbol
RESET
+V ref
V DD
C PH
R PH
C OP
DTA
ICO
SD
Strike detection
Supply voltage
Preheat timing
sweep timing
Preheat and
Steady state
current input
Master reset
frequencies
adjustment
adjustment
Dead Time
Frequency
frequency
Function
reference
Oscillator
operating
capacitor
capacitor
capacitor
resistors
Voltage
output
Adjust
Strike
input
input
input
This pin provides the DC supply to the circuit. The voltage is internally clamped by a zener
connected to the ground. It is NOT allowed to use a DC low impedance power supply to feed this
pin, but limiting the current by an external resistor is mandatory. It is recommended to damp this pin
to ground by an electrolytic capacitor connected close to pin 1.
This pin provides a +7V voltage reference derived from the internal bandgap. The +Vref can supply
up to 25 mA and shall be decoupled to ground by a 220nF ceramic capacitor
This capacitor sets two timings: filaments preheat time (t PH ) and strike sequence recycle time (t SK ).
It is charged with a constant current and cares must be observed to minimize the leakage current
at this pin to get the expected timing. Typically, a 0.47 F capacitor will give a 2 seconds
pre–heating time and a 125 ms strike sequence recycle time. (See details given by figure 9)
The R PH resistor together with R ENDSWEEP and C OP defines the frequency used to preheat the
filaments (f PH = f 1 ). R ENDSWEEP defines the strike frequency (f ENDSWEEP = f 2 ). During the sweep
timing, the frequency will sweep from the high pre–heating f 1 to the low strike f 2 values. Normally,
f 1 is far from the LC resonance but f 2 is close enough to generate the high voltage across the
fluorescent tube. (See details given by figure 9)
This timing define the sweep time from f 1 to f 2 . Since the timing capacitor is charged with a low
constant current, cares must be observed to minimize the leakage current at this pin to get the
expected timing. Since this capacitor is charged through resistor R PH , the voltage rises according
to an exponential and the frequency shifts with the same law.
This pin defines the steady state operation frequency (f 3 = f OP ) of the controller. Since this timing
capacitor is charged with a low constant current, cares must be observed to minimize the leakage
current at this pin to get the expected frequency. Film type capacitor are recommended
(polycarbonate).
Since the circuit uses a Current Controlled Oscillator (ICO), the current forced into this pin will
control the operating frequency. The allowable current range is from 1 A to 500 A. The +Vref
output can be used to provide the voltage across R OP . An auxiliary voltage source can be used to
implement a dimming function.
This pin provides an access to the internal timing system to adjust the dead time between the gate
drive of the High and Low power switches connected, respectively, to pin V HO and V LO .
This pin drives a comparator, with an internal fixed reference, and acknowledges the tube strike.
When a negative going slope (across the internal reference) is detected, the system considers the
lamp has struck and the oscillator jumps from the present frequency value, which is within the
window defined by R PH and R ENDSWEEP to the steady state value defined by R OP . If no negative
going slope is detected on this pin, the system will repeat the sweep and strike sequence four
times, then stops. The circuit will re–start from either a RESET, or by pulling +V DD to ground. The
input signal can be either a logic level or an analog voltage ramping up from zero to +Vref followed
by a negative going slope to zero. In any case, the positive pulse width must be 1 s minimum. The
pcb layout must be designed to minimize the noise at this pin. (See details given by figures 8, 9, &
10)
Forcing a logic zero to this pin (HCMOS low level) will reset the circuit, initializing a frequency sweep
and lamp strike sequence. The master reset does not include the pre–heating timing. The minimum
pulse width requested is 10 s to guarantee a reset state. However, this pin has no built in filtering
and a shorter pulse may initialize a reset sequence: it is the responsibility of the designer to make
sure that no noise or parasitic pulse are developed at the RESET input. A full re–start of the
sequence, including the pre–heating time, can be initialized by pulling the +V DD pin to ground. In this
case, +V DD and RESET must be simultaneously released to a high state. When RESET is asserted
low (active) both outputs MOS are biased in the off condition. An internal 20 A pull up current forces
the pin to logic one, allowing the designer to left this pin open if the RESET function is not used. In
order to avoid any uncontrolled state of the output drivers, it is recommended to set up a 10ms low
level at pin 10. The reset is activated in less than 10 microsecond, but releasing this pin while the Vcc
supply is high (above 300V) can generate a random operation, depending upon the dv/dt coming
from the power supply.
PIN FUNCTION DESCRIPTION
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MC33157
4
Description