adm6993 Infineon Technologies Corporation, adm6993 Datasheet - Page 31

• Manufacturer Part Number: adm6993
• Description: Adm6993/x Hdlc To Fast Ethernet Converter
• Manufacturer: Infineon Technologies Corporation

Zero Insertion The data in the packet read from the BUFFER is checked for the number of contiguous ones prior
to the transmission. A zero is inserted into the transmitted bit stream after five contiguous ones are detected,
excluding Flags or Abort characters. By this, HDLC can avoid the confusion between flag and data, which has the
same value with flag.
Cyclic Redundancy Check (CRC) Generation The Frame Check Sequence (FCS) consists of 16 bits
immediately preceding the closing flag. The 16-bit FCS detects data errors through the use of a cycle redundancy
check (CRC) code. When all user data is transmitted, the calculated value is transmitted after the last data byte,
and encloses the frame with a closing flag. The CRC check polynomials are as follows:
CRC-16: X
3.7
The ADM6993/X can be reset either by hardware or software. A hardware reset is accomplished by applying a
negative pulse, with the duration of at least 100 ms to the RC pin of the ADM6993/X during normal operation to
guarantee internal SSRAM is reset well.
Hardware reset operation samples the pins and initializes all registers to their default values. This process includes
re-evaluation of all hardware configurable registers. A hardware reset affects all embedded PHYs in the device.
Software reset can reset all embedded PHY and it does not latch the external pins nor reset the registers to their
respective default value. This can be achieved by writing FF to EEPROM Reg.3F
Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of
ADM6993/X. Some of these pins are used as output ports after reset operation.
Care must be taken to ensure that the configuration setup will not interfere with normal operations. Dedicated
configuration pins can be tied to VCC or Ground directly. Configuration pins multiplexed with logic level output
functions should be either weakly pulled up or weakly pulled down through external resistors.
3.7.1
To write data into desired EEPROM Register via EEPROM interface:
If external EEPROM 93C46 or 93C66 exists, any WRITE programming instructions after EWEN instruction be
executed can be updated effectively on EEPROM content and ADM6993/X internal mapping register on the same
time.
If no external EEPROM exists, EECS/EECK/EEDI must be kept tri-state at least 100ms after hardware reset. Any
WRITE programming instructions after EWEN instruction be executed can be updated effectively on ADM6993/X
internal mapping register. Please notice that ADM6993/X can only identify 93C66-programming instructions if no
external EEPROM.
Data Sheet
16
+X
Reset Operation
Write EEPROM Register via EEPROM Interface
12
+X
5
+1
31
H
.
Function Description
Rev 1.11, 2005-11-28
ADM6993/X