lan8720 Standard Microsystems Corp., lan8720 Datasheet
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... Digital Video Recorders IP and Video Phones Wireless Access Points Digital Televisions Digital Media Adaptors/Servers Gaming Consoles POE Applications SMSC LAN8720/LAN8720i LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Key Benefits High-Performance 10/100 Ethernet Transceiver — Compliant with IEEE802.3/802.3u (Fast Ethernet) — ...
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... LAN8720-CP-TR FOR 24-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +85°C TEMP) LAN8720i-CP-TR FOR 24-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO +85°C TEMP) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Transmit Data Across the MII/RMII Interface 4.4.2 Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.3 10M Transmit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 10Base-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.1 10M Receive Input and Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.2 Manchester Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.3 10M Receive Data Across the MII/RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.4 Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 MAC Interface 4.6.1 RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7.1 REF_CLK In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7.2 REF_CLK OUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SMSC LAN8720/LAN8720i 3 DATASHEET Revision 1.0 (04-15-09) ...
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... Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.4 DC Characteristics - Input and Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.1.1 RMII Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.1.2 Power Supply Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.1.3 Twisted-Pair Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2 Magnetics Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 4 DATASHEET Datasheet SMSC LAN8720/LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SMSC LAN8720/LAN8720i 5 DATASHEET Revision 1.0 (04-15-09) ...
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... Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4.4 External 50MHz clock sources the REF_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 4.6 LAN8720 Sources REF_CLK from External 25MHz Source . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 4.7 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 4 ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet List of Tables Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.2 RMII Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.3 LED Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.4 Management Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.5 General Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.6 10/100 Line Interface Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3 ...
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... Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK OUT Table 6.10 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.11 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.12 LAN8720/LAN8720i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.1 Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.2 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7 ...
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... Figure 1. available in both extended commercial and industrial temperature operating versions. The LAN8720/LAN8720i interfaces to the MAC layer using a variable voltage digital interface via the RMII interface. The digital interface pins are tolerant to 3.6V. The LAN8720/LAN8720i implements Auto-Negotiation to automatically determine the best possible speed and duplex mode of operation ...
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... The LAN8720 will begin normal operation following reset, and no register access is required. The initial configuration may be selected with configuration pins as described in register-selectable configuration options may be used to further define the functionality of the transceiver. For example, the device can be set to 10BASE-T only. The LAN8720 supports both IEEE 802.3-2005 compliant and vendor-specific register functions. Revision 1.0 (04-15-09) ...
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... Control Management SMI Control TXD[1:0] TXEN 100M Rx Logic RXD[1:0] Receive Section RXER 10M Rx Logic CRS_DV MDC MDIO Figure 1.2 LAN8720/LAN8720i Architectural Overview SMSC LAN8720/LAN8720i 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- Clock Digital Data Recovery Equalizer 100M PLL Squelch & ...
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... Chapter 2 Pin Configuration 2.1 Package Pin-out Diagram and Signal Table VDD2A LED2/nINTSEL LED1/REGOFF XTAL2 XTAL1/CLKIN VDDCR Figure 2.1 LAN8720/LAN8720i 24-QFN Pin Assignments (TOP VIEW) Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 1 18 TXD1 SMSC 2 17 TXD0 LAN8720 TXEN LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout PIN NO. PIN NAME 1 VDD2A 2 LED2/nINTSEL 3 LED1/REGOFF 4 XTAL2 5 XTAL1/CLKIN 6 VDDCR 7 RXD1/MODE1 8 RXD0/MODE0 9 VDDIO 10 RXER/PHYAD0 11 CRS_DV/MODE2 12 MDIO SMSC LAN8720/LAN8720i PIN NO. PIN NAME 13 14 nINT/REFCLKO ...
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... When connected to a load that must be pulled high or low, an external resistor must be added. Note: The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V, as shown in Table 7.1. Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 3.1. Table 3.1 Buffer Types DESCRIPTION 14 DATASHEET Datasheet . LAN8720/LAN8720i SMSC LAN8720/LAN8720i ...
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... NAME PIN # TYPE LED1/ 3 IOPD REGOFF SMSC LAN8720/LAN8720i Table 3.2 RMII Signals 24-QFN DESCRIPTION Transmit Data 0: The MAC transmits data to the PHY using this signal in all modes. Transmit Data 1: The MAC transmits data to the PHY using this signal in all modes Transmit Enable: Indicates that valid data is presented on the TXD[1:0] signals, for transmission ...
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... LED2 – Link speed LED Indication. This signal is mux’d with REFCLKO. Clock Input: Crystal connection or external clock input. Clock Output: Crystal connection. Float this pin when an external clock is driven to XTAL1/CLKIN. External Reset: Input of the system reset. This signal is active LOW. 16 DATASHEET Datasheet SMSC LAN8720/LAN8720i ...
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... VDD1A 19 P VDD2A 1 P VSS FLAG GND SMSC LAN8720/LAN8720i DESCRIPTION Transmit/Receive Positive Channel 1. Transmit/Receive Negative Channel 1. Transmit/Receive Positive Channel 2. Transmit/Receive Negative Channel 2. Table 3.7 Analog References 24-QFN DESCRIPTION External 1% Bias Resistor. Requires an 12.1k resistor to ground connected as described in the Analog Layout Guidelines. The nominal voltage is 1.2V and therefore the resistor will dissipate approximately 1mW of power ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PLL 4B/5B 25MHz RMII by 4 bits Encoder NRZI MLT-3 NRZI MLT-3 Converter Magnetics MLT-3 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 18 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Tx Driver RJ45 CAT-5 MLT-3 SMSC LAN8720/LAN8720i ...
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... First nibble of SSD, translated to “0101” following IDLE, else RXER 10001 K Second nibble of SSD, translated to “0101” following J, else RXER 01101 T First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RXER SMSC LAN8720/LAN8720i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 ...
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... Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 20 DATASHEET Datasheet TRANSMITTER INTERPRETATION Sent for falling TXEN Sent for rising TXER INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN8720/LAN8720i ...
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... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN8720/LAN8720i PLL 4B/5B ...
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... SIGDET becomes false. RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII mode). Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support 22 DATASHEET Datasheet SMSC LAN8720/LAN8720i ...
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... The MAC controller drives the transmit data onto the TXD BUS. For MII, when the controller has driven TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide 2.5MHz data. SMSC LAN8720/LAN8720i 5 5 ...
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... Section 5.3.2, "Collision Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the LAN8720/LAN8720i. TXD[1:0] shall be “00” to indicate idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... Reference Clock - (RMII references usually define this signal as REF_CLK) 4.6.1.1 CRS_DV - Carrier Sense/Receive Data Valid The CRS_DV is asserted by the LAN8720/LAN8720i when the receive medium is non-idle. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected, carrier is said to be detected ...
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... In the first mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. This is the traditional system configuration when using RMII, and is described in advanced feature of the LAN8720 allows a low-cost 25MHz crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and is described in Revision 1 ...
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... The MAC must be capable of operating with an external clock to take advantage of this feature as shown in The LAN8720 is a small size, low pin count device. In order to optimize package size and cost, the REFCLKO pin is multiplexed with the nINT pin. Therefore, in this specific mode of operation, the nINT pin is disabled since REFCLKO is used to provide the 50MHz clock to the MAC ...
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... REF_CLK 2 Interface Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal In some system architectures, a 25MHz clock source is available. The LAN8720 can be used to generate the REF_CLK to the MAC as shown in Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support LAN8720 MDIO 10/100 PHY ...
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... The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The LAN8720 uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the LAN8720 uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK ...
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... Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8720/LAN8720i does not support “Next Page” capability. Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support ...
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... Parallel Detection If the LAN8720/LAN8720i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... REF_CLK Out Mode LED2/nINTSEL = 1 REF_CLK In Mode When configured for REF_CLK Out Mode, the LAN8720 generates the 50MHz RMII REF_CLK and the interrupt is not available in this mode. The nINTSEL pin is shared with the LED2 pin. The LED2 output will automatically change polarity based on the presence of an external pull-down resistor ...
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... To set REGOFF without LEDs, pull-up the pin with an external resistor to VDDIO to disable the regulator. See Figure 4.9. REGOFF = 1 (Regulator OFF) LED output = active low VDD2A 10K ~270 ohms LED1/REGOFF Figure 4.9 REGOFF Configuration on LED1 SMSC LAN8720/LAN8720i nINTSEL = 0 LED output = active high 10K Figure 4.8 nINTSEL Strapping on LED2 REGOFF = 0 LED output = active high 33 DATASHEET LED2/nINTSEL ~270 ohms ...
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... Variable Voltage I/O The Digital I/O pins on the LAN8720/LAN8720i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10 +3.3V+10%. The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance of ± 10%. Varying the voltage up or down, after the transceiver has completed power- on reset can cause errors in the transceiver operation ...
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... Start of OP Preamble Frame Code Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle SMSC LAN8720/LAN8720i Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address ...
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Chapter 5 SMI Register Mapping Reset Loopback Speed A/N Select Enable 100Base 100Base 100Base 10Base- T -T4 -TX -TX Full Half Full Duplex Duplex Duplex PHY ID ...
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Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended Next Reserved Remote Reserved Page Fault Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault ...
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Table 5.10 Mode Control/ Status Register 17: Vendor-Specific RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved Reserved MIIMODE Table 5.14 Symbol ...
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Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL Reserved CH_SELECT Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific Reserved ...
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... X = Either Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Table 5.20 SMI Register Mapping DESCRIPTION 40 DATASHEET Datasheet Group Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8720/LAN8720i ...
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... Reserved 1.5 Auto-Negotiate 1 = auto-negotiate process completed 0 = auto-negotiate process not completed Complete SMSC LAN8720/LAN8720i Table 5.21 Register 0 - Basic Control DESCRIPTION when setting this bit do not set other bits in this register. The configuration (as described in Section 5.3.9.2) is set from the register bit values, and not from the mode pins. ...
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... Symmetric PAUSE 10= Asymmetric PAUSE toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local device 42 DATASHEET Datasheet MODE DEFAULT MODE DEFAULT RW 0007h MODE DEFAULT RW 30h RW 0Fh RW DEVICE REV MODE DEFAULT R/W 00 SMSC LAN8720/LAN8720i ...
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... Duplex 5.7 100Base-TX 5.6 10Base-T Full Duplex 5.5 10Base-T 5.4:0 Selector Field SMSC LAN8720/LAN8720i DESCRIPTION able ability This Phy does not support 100Base-T4 with full duplex full duplex ability able ability 1 = 10Mbps with full duplex 10Mbps with full duplex ability ...
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... Section 5.3.8.2. This mode works even if MII Isolate (0.10) is set. Write as 0, ignore on read. 44 DATASHEET Datasheet MODE DEFAULT MODE DEFAULT 0001 RO 0 MODE DEFAULT SMSC LAN8720/LAN8720i ...
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... MODE 18.4:0 PHYAD Table 5.31 Register 26 - Symbol Error Counter ADDRESS NAME 26.15:0 Sym_Err_Cnt SMSC LAN8720/LAN8720i DESCRIPTION Alternate Interrupt Mode Primary interrupt system enabled (Default Alternate interrupt system enabled. See Section 5.2, "Interrupt Management," on page Write as 0, ignore on read PHY disregards PHY address in SMI access write normal operation ...
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... Auto-Negotiation LP Acknowledge 0 = not source of interrupt 1 = Parallel Detection Fault 0 = not source of interrupt 46 DATASHEET Datasheet MODE DEFAULT RW, 0 NASR RW 000000 XXXXb MODE DEFAULT RW N/A MODE DEFAULT SMSC LAN8720/LAN8720i ...
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... GPO[2:0] 31.6 Enable 4B5B 31.5 Reserved 31.4:2 Speed Indication 31.1 Reserved 31.0 Scramble Disable SMSC LAN8720/LAN8720i DESCRIPTION 1 = Auto-Negotiation Page Received 0 = not source of interrupt Ignore on read. Table 5.35 Register 30 - Interrupt Mask DESCRIPTION Write as 0; ignore on read interrupt source is enabled 0 = interrupt source is masked Write as 0; ignore on read DESCRIPTION Write as 0, ignore on read. ...
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... It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30. The Interrupt system on the SMSC The LAN8720 has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT ...
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... Miscellaneous Functions 5.3.1 Carrier Sense The carrier sense is output on CRS. CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The LAN8720 asserts CRS based only on receive activity whenever the transceiver is either SMSC LAN8720/LAN8720i EVENT TO INTERRUPT SOURCE ASSERT nINT 17.1 ENERGYON Rising 17 ...
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... The user can disable this pulse by setting bit 11 in register 27. 5.3.3 Isolate Mode The LAN8720 data paths may be electrically isolated from the MII by setting register 0, bit logic one. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does respond to management transactions. ...
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... Section 4.10 and Section The LED1 output is driven active whenever the LAN8720 detects a valid link, and blinks when CRS is active (high) indicating activity. The LED2 output is driven active when the operating speed is 100Mbit/s. This LED will go inactive when the operating speed is 10Mbit/s or during line isolation (register 31 bit 5). ...
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... Digital Ethernet Transceiver Figure 5.2 Far Loopback Block Diagram 5.3.8.3 Connector Loopback The LAN8720/LAN8720i maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 5.1.The near-end loopback mode is enabled ...
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... The PHY address can be written (after SMI communication at some address is established) using the 10/100 Special Modes register (bits18.[4:0]). The PHYAD0 hardware configuration pin is multiplexed with the RXER pin. The LAN8720 may be configured to disregard the PHY address in SMI access write by setting the register bit 17.3 (PHYADBP). 5.3.9.2 Mode Bus – ...
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... Table 5.39 MODE[2:0] Bus Table 5.30) must be configured Table 5.40 Pin Names for Mode Bits MODE BIT PIN NAME MODE[0] RXD0/MODE0 MODE[1] RXD1/MODE1 MODE[2] CRS_DV/MODE2 54 DATASHEET Datasheet DEFAULT REGISTER BIT VALUES REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] 0000 N/A 0001 N/A 1000 N/A 1001 N/A 1100 0100 1100 0100 N/A N/A X10X 1111 Table 5.40. SMSC LAN8720/LAN8720i ...
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... Data In - MDIO PARAMETER DESCRIPTION T1.1 MDC minimum cycle time T1.2 MDC to MDIO (Read from PHY) delay T1.3 MDIO (Write to PHY) to MDC setup T1.4 MDIO (Write to PHY) to MDC hold SMSC LAN8720/LAN8720i T 1.1 T 1.2 Valid Data (Read from PHY) T 1.3 1.4 Valid Data (Write to PHY) Figure 6.1 SMI Timing Diagram Table 6.1 SMI Timing Values ...
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... RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN) The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high on the LAN8720. In this mode, a 50MHz clock must be provided to the LAN8720 CLKIN pin. For more information on REF_CLK IN Mode, see 6.2.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN) 6.2.1.1 100M RMII Receive Timing (50MHz REF_CLK IN) ...
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... Figure 6.3 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN) Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T8.1 Transmit signals required setup to rising edge of CLKIN T8.2 Transmit signals required hold after rising edge of CLKIN CLKIN frequency SMSC LAN8720/LAN8720i T T 8.1 8.2 Valid Data MIN TYP MAX 4 2 ...
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... Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T9.1 Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support T 9.1 Valid Data MIN TYP MAX UNITS DATASHEET Datasheet NOTES ns MHz SMSC LAN8720/LAN8720i ...
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... Figure 6.5 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN) Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION T10.1 Transmit signals required setup to rising edge of CLKIN T10.2 Transmit signals required hold after rising edge of CLKIN CLKIN frequency SMSC LAN8720/LAN8720i T T 10.1 10.2 Valid Data MIN TYP MAX UNITS 4 ...
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... RMII 10/100Base-TX/RX Timings (50MHz REF_CLK OUT) The 50MHz REF_CLK OUT timing applies to the case when LED/nINTSEL is pulled-low on the LAN8720. In this mode, a 25MHz crystal or clock oscillator must be provided to the LAN8720. For more information on 50MHz REF_CLK OUT mode, see 6.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK OUT) 6 ...
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... Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK OUT) Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION T12.1 Transmit signals required setup to rising edge of REFCLKO T12.2 Transmit signals required hold after rising edge of REFCLKO REFCLKO frequency SMSC LAN8720/LAN8720i T T 12.1 12.2 Valid Data MIN TYP MAX 7 2.5 ...
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... Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION T13.1 Output delay from rising edge of REFCLKO to receive signals output valid REFCLKO frequency Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support T 13.1 Valid Data MIN TYP MAX UNITS 1 DATASHEET Datasheet NOTES ns MHz SMSC LAN8720/LAN8720i ...
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... Transmit signals required hold after rising edge of REFCLKO CLKIN frequency 6.4 RMII CLKIN Requirements Table 6.10 RMII CLKIN (REF_CLK) Timing Values PARAMETER DESCRIPTION CLKIN frequency CLKIN Frequency Drift CLKIN Duty Cycle CLKIN Jitter SMSC LAN8720/LAN8720i T T 14.1 14.2 Valid Data MIN TYP MAX UNITS 7 2.5 50 ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support T 11 11.2 11.3 T 11.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values MIN TYP MAX 100 200 10 20 800 64 DATASHEET Datasheet UNITS NOTES clock cycles for 25 MHz clock or 40 clock cycles for 50MHz clock SMSC LAN8720/LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.6 Clock Circuit LAN8720/LAN8720i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See for the recommended crystal specifications. ...
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... TYP MAX ESD PERFORMANCE ±5 ±15 ±15 LATCH-UP PERFORMANCE 150 66 DATASHEET Datasheet UNITS COMMENT V V Table 7.6 V °C/W °C Extended commercial temperature components Industrial temperature components UNITS COMMENTS kV Device kV 3rd party system test kV 3rd party system test mA SMSC LAN8720/LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet no change in operation or performance due to the event. All pins on the LAN8720 provide +/-5kV HBM protection. 7.1.1.2 IEC61000-4-2 Performance The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down ...
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... VDDCR POWER POWER PINS(MA) PIN(MA) Max 27.7 20 25.8 18.1 Min 21.2 14.1 68 DATASHEET Datasheet VDDIO TOTAL TOTAL POWER CURRENT POWER PIN(MA) (MA) (MW) 0.6 48.1 158.7 0.5 44.7 147.5 0.3 40.1 95.3 Note 7.1 0.6 23.3 76.9 0.5 21.2 70 0.3 19.7 41.3 Note 7.1 0.2 7.4 24.4 0.2 6.2 20.4 0 5.8 15.2 Note 7.1 0.2 3.4 11.2 0.2 2.3 7 Note 7.1 Section 5.3.5 for a description Section 4.7.2 VDDIO TOTAL TOTAL POWER CURRENT POWER PIN(MA) (MA) (MW) 6.3 54 178.2 5.8 49.7 164 2.9 38.2 92.1 Note 7.3 SMSC LAN8720/LAN8720i ...
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... Note: The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A, or from an external 1.2V supply when the internal regulator is disabled. Note 7.3 This is calculated with full flexPWR features activated: VDDIO = 1.8V and internal regulator disabled. Note 7.4 Current measurements do not include power applied to the magnetics or the optional external LEDs. SMSC LAN8720/LAN8720i Max 9.9 12.8 8.8 11.3 Min 7.1 9 ...
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... 0.4 * VDDIO 0.4 * VDDIO 0.4 * VDDIO - 0.4 * VDDIO 0.4 * VDDIO - DATASHEET Datasheet I V ( +0.4 VDDIO – +0 +0.4 VDDIO – +0 +0.4 VDDIO – +0 +0.4 VDDIO – +0 +0.4 VDDIO – +0 +0.4 VDDIO – +0 +0.4 3.6 SMSC LAN8720/LAN8720i ...
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... XTAL2 Note 7.5 These levels apply when a 0-3.3V Clock is driven into XTAL1/CLKIN and XTAL2 is floating. The maximum input voltage on XTAL1/CLKIN is VDD2A + 0.4V. Table 7.11 Internal Pull-Up / Pull-Down Configurations NAME TXEN RXD0/MODE0 SMSC LAN8720/LAN8720i Table 7.7 LAN Interface Signals “10BASE-T Transceiver Characteristics,” on page Table 7 ...
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... PPH V -950 - -1050 PPL 102 SS T 3 0.5 RFS 1.4 SYMBOL MIN TYP V 2.2 2.5 OUT V 300 420 DS 72 DATASHEET Datasheet UNITS NOTES mVpk Note 7.6 mVpk Note 7.6 % Note 7.6 nS Note 7.6 nS Note 7 Note 7 Note 7.8 MAX UNITS NOTES 2.8 V Note 7.9 585 mV SMSC LAN8720/LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 8 Application Notes 8.1 Application Diagram The LAN8720 requires few external components. The voltage on the magnetics center tap can range from 2.5 - 3.3V. 8.1.1 RMII Diagram RMII MDIO MDC nINT TXD[1:0] 2 TXEN RXD[1:0] 2 RXER LED[2:1] ...
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... Analog Supply 3.3V LAN8720 24-QFN 6 VDDCR VDD1A 9 VDDIO VDD2A C BYPASS RBIAS 15 nRST VSS 49.9 Resistors Magnetic Supply 2.5 - 3.3V Magnetics C BYPASS Figure 8.5 Copper Interface Diagram 74 DATASHEET Datasheet Power to magnetics interface BYPASS 1 C BYPASS 24 12k RJ45 1000 SMSC LAN8720/LAN8720i ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 8.2 Magnetics Selection For a list of magnetics selected to operate with the SMSC LAN8720, please refer to the Application note “AN 8-13 Suggested Magnetics”. http://www.smsc.com/main/appnotes.html#Ethernet%20Products SMSC LAN8720/LAN8720i 75 DATASHEET Revision 1.0 (04-15-09) ...
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... Chapter 9 Package Outline Figure 9.1 LAN8720/LAN8720i-EZK 24-QFN Package Outline 0.9 mm Body (Lead-Free) Table 9.1 24 Terminal QFN Package Parameters MIN NOMINAL A 0. 3.85 D1 3.55 D2 2.40 E 3.85 E1 3.55 E2 2.40 L 0.30 e 0.50 BSC b 0.18 ccc ~ Notes: 1. Controlling Unit: millimeter. 2. Dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the terminal tip. Tolerance on the true position of the leads is ± ...
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... Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation SMSC LAN8720/LAN8720i 77 DATASHEET Revision 1.0 (04-15-09) ...
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... Note: Standard reel size is 4000 pieces per reel. Revision 1.0 (04-15-09) Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Figure 9.2 Reel Dimensions 78 DATASHEET Datasheet SMSC LAN8720/LAN8720i ...