adm8513 Infineon Technologies Corporation, adm8513 Datasheet

no-image

adm8513

Manufacturer Part Number
adm8513
Description
Usb-to-10/100 Mbps Ethernet Lan Controller
Manufacturer
Infineon Technologies Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADM8513
Manufacturer:
CYPRESS
Quantity:
784
Part Number:
ADM8513
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
adm8513X-AD-T-1
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
adm8513X-AD-T-1AD
Quantity:
30
D a t a S h e e t , R e v . 1 . 2 1 , D e c . 2 0 0 5
A M D 8 5 1 3 / X
U S B - t o - 1 0 / 1 0 0 M b p s E th e r n e t L A N C o n t r o l l e r
C o m m u n i c a t i o n s
N e v e r
s t o p
t h i n k i n g .

Related parts for adm8513

adm8513 Summary of contents

Page 1

...

Page 2

Edition 2005-12-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...

Page 3

USB-to-10/100 Mbps Ethernet LAN Controller Revision History: 2005-12-05, Rev. 1.21 Previous Version: Page/Date Subjects (major changes since last revision) 2001-12 Rev. 0.1: Preliminary 2002-01 Rev. 1.0: Rearrange 2002-06 Rev. 1.1: 1.VAARef I/O is power pin, not input pin in P.7 ...

Page 4

... Get Descriptor (Device) Total 18-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.10 Get Descriptor (Configuration) Total 39-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.11 Get Descriptor (String) Index 0, LanguageID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.12 Get Descriptor (String) Index 1, Manufacture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.13 Get Descriptor (String) Index 2, Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.14 Get Descriptor (String) Index 3, Serial No 5.1.15 Get Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Sheet 4 ADM8513 Data Sheet Table of Contents Rev. 1.21, 2005-12-05 ...

Page 5

... EEPROM Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2 GPIO Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.2 USB Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.3 EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10 EEPROM Interface & Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12 Appendix Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Sheet 5 ADM8513 Data Sheet Table of Contents Rev. 1.21, 2005-12-05 ...

Page 6

... Placement 1 84 Figure 8 Placement 2 84 Figure 9 Trace Routing 1 85 Figure 10 Trace Routing 2 85 Figure 11 Trace Routing 3 86 Figure 12 Power and Ground 1 86 Figure 13 Power and Ground 2 86 Figure 14 Power and Ground 3 87 Data Sheet 6 ADM8513 Data Sheet List of Figures Rev. 1.21, 2005-12-05 ...

Page 7

... Table 40 Setup Stage 22 Table 41 Configuration Descriptor 1 22 Table 42 Configuration Descriptor 2 22 Table 43 Interface 0 Descriptor 22 Table 44 EP1 Descriptor 22 Table 45 EP2 Descriptor 22 Table 46 EP3 Descriptor 22 Table 47 Setup Stage 23 Table 48 Data Stage 23 Table 49 Setup Stage 23 Data Sheet 7 ADM8513 Data Sheet List of Tables Rev. 1.21, 2005-12-05 ...

Page 8

... Table 77 USB Interface DC Specification 74 Table 78 EEPROM Interface DC Specification 75 Table 79 GPIO Interface DC Specification 75 Table 80 GPIO Interface DC Specification 76 Table 81 EEPROM Interface Timing 76 Table 82 EEPROM Interface 77 Table 83 EEPROM Example 78 Table 84 Dimensions for 48 Pin LQFP Package 82 Data Sheet 8 ADM8513 Data Sheet List of Tables Rev. 1.21, 2005-12-05 ...

Page 9

... LED0: speed indication for 10Mbps or 100Mbps. – LED1: link indication. – LED2: full duplex indication. • Support Power Save Function @ USB suspend mode Data Sheet Package Ordering Number P-LQFP-48-5 Q67801H 62A101 PG-LQFP-48-5 Q67801H 98A101 9 ADM8513 Data Sheet Product Overview 1) Rev. 1.21, 2005-12-05 ...

Page 10

... Provides 48-pin LQFP package – 3.3 V power supply with 5 V/3.3 V I/O tolerance • Support Driver – Win98/ME/2000/XP – Linux driver, WinCE 3.0&4.0 driver – Manufacturing test utilities: – EEPROM Burn-in program – MFG testing program Data Sheet 10 ADM8513 Data Sheet Product Overview Rev. 1.21, 2005-12-05 ...

Page 11

... Interface Description 2.1 Pin Assignment Diagram Pin Diagram ADM8513/X. VDD33 EECS EESK EEDI EEDO VDD33 Vss GPIO1 GPIO0 POREN# NC Vss Figure 1 Pin Diagram 2.2 Pin Description by Function Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. ...

Page 12

... Data Sheet Pin Buffer Function Type Type I Input Clock 48 MHz clock input from crystal or oscillator. O Output for Crystal I External Hardware Reset Input Schmitt-trigger, internal pull high. I/O USB Data Minus pin I/O USB Data Plus Pin 12 ADM8513 Data Sheet Interface Description Rev. 1.21, 2005-12-05 ...

Page 13

... Active low indicates 100Base-TX, active high indicates 10 BaseT. O LED display for link and activity status. Active low when link is established. O LED display for Full Duplex or Collision status. Active low indicates full duplex, high indicates collision in half duplex. 13 ADM8513 Data Sheet Interface Description ) B Rev. 1.21, 2005-12-05 ...

Page 14

... EEPROM. CMOS I/O with 5 V tolerant, 2mA Pin Buffer Function Type Type I/O General Purpose Input/Output Pins These pins are used as general purpose Input/Output pins and offset 0A[ EEPROM. Default is internal pull-low I Test Pins X Test Pins 14 ADM8513 Data Sheet Interface Description Rev. 1.21, 2005-12-05 ...

Page 15

... PWR +3.3V Power Ground for PHY PWR +3.3V for Transmitter PWR GND for Transmitter PWR +3.3V for Receiver PWR GND for Receiver SRAM USB Command RX & EP FIFO Controller Decoder 2K TX FIFO 15 ADM8513 Data Sheet Interface Description RJ45 10/100 M Ethernet Ph 10/100M Ethernet MAC Rev. 1.21, 2005-12-05 ...

Page 16

... Ethernet speed. 4 USB Device Endpoint Operation 4.1 Endpoint 0 Endpoint charge of response to standard USB commands and vendor specific commands. Internal register settings are also via this endpoint. The response to each command is described in section 6. Data Sheet 16 ADM8513 Data Sheet Function Description Rev. 1.21, 2005-12-05 ...

Page 17

... Indicates received packet length > 1518 bytes. runt_pkt Indicates received packet length < 64 bytes. crc_err Indicates CRC check error. dribble_bit Indicates packet length is not integer multiple of 8- bit. reserved reserved 17 ADM8513 Data Sheet USB Device Endpoint Operation 1/10/100 MAC Layer Ethernet (64 to 1514 bytes) Packet Rev. 1.21, 2005-12-05 ...

Page 18

... H H Offset6(1B) Packet number in RX FIFO (Reg82 ) H RegIndex[7: Data Sheet USB Commands The Following Packets Ethernet packet 1/10/100 MAC Layer Ethernet (64 to 1514 bytes) Packet Offset3 Offset4 rx_lostpkt(Reg2E ) rx_lostpkt(Reg2F H Offset7(1B) 7’b00, length error Length Low Length High Rev. 1.21, 2005-12-05 ADM8513 ) H ...

Page 19

... Offset1(1B) {RegIndex+1) RegIndex[7:0] 00 Offset2(1B) {RegIndex+2} wValue wIndexLow wIndexHigh H(1B) (1B) (1B and data from ADM8513 Data Sheet USB Commands Offset2(1B) {RegIndex+2) Length Low Length High Offset3(1B) {RegIndex+3} wLength wLength L(1B) H(1B Rev. 1.21, 2005-12-05 ...

Page 20

... Get Status (EP1) Bulk In Data Sheet Offset2(1B) 13 wValue(2B) wIndex(2B D[1]: Remote Wakeup Register of remote_wakeup wValue(2B) wIndex(2B wValue(2B) wIndex L(1B) wIndex H(1B) wLength D[0]: Halt Register of ep0_halt 20 USB Commands wLength L(1B) wLength H(1B D[0]:Self Powered 1 wLength L(1B) wLength H(1B L(1B Rev. 1.21, 2005-12-05 ADM8513 Data Sheet wLength H(1B) 0 ...

Page 21

... Register of ep1_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength 0 02 D[0]: Halt register of ep2_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength 0 83 D[0]: Halt register of ep3_halt wValue L(1B) wValue H(1B) wIndex(2B USB Commands L(1B L(1B L(1B wLength L(1B) 0 Length low Rev. 1.21, 2005-12-05 ADM8513 Data Sheet wLength H(1B) 0 WLength H(1B) 0 wLength H(1B) 0 wLength H(1B) Length high ...

Page 22

... High Low 01 Offset 17 (no. of no.) config) 03 wLength L(1B) 0 Length low Offset 3 Offset 4 (TotalLength) High (NumInterface) 00 Offset 8(MaxPower) max_pwr(1 B Offset 6 Offset 7 (IntfSubCl (IntfProto ass) col) ) E0 Rev. 1.21, 2005-12-05 ADM8513 Data Sheet Offset 7 (EP0 MaxPktSize) 8 wLength H(1B) Length high ) Offset 8 (StringInd ex) 00 ...

Page 23

... Offset 4 Offset 6 (MaxPktSize) (Interval) High ) 00 Offset 5 Offset 6 (MaxPktSize) (Interval) High ) 00(1 ) ep3_interval wLength Low(1B) 0000 Length Low Offset3 (LanguageID wLength Low(1B) 0904 Length Low String Rev. 1.21, 2005-12-05 ADM8513 Data Sheet ) wLength High(1B) Length High wLength High(1B) Length High ...

Page 24

... USB Commands wLength Low(1B) 0904 Length Low String wLength Low(1B) 0904 Length Low String wLength wLength Low(1B) High(1B wLength wLength Low(1B) High(1B Rev. 1.21, 2005-12-05 ADM8513 Data Sheet wLength High(1B) Length High wLength High(1B) Length High ...

Page 25

... Table 62 Setup Stage BmReq bReq 02 03 Data Sheet wValue L(1B) WValue H(1B wValue L(1B) WValue H(1B wValue(2B) WIndex L(1B) 0000 EP no wValue(2B) WIndex H(1B) 0000 ADM8513 Data Sheet USB Commands wIndex(2B) wLength(2B wIndex(2B) wLength(2B wIndex L(2B) WLength(2B wIndex H(2B) WLength(2B Rev. 1.21, 2005-12-05 ...

Page 26

... Pause Timer RPNBFC Receive Packet Number Based Flow Control ORFBFC Occupied Receive FIFO Based Flow Control EP1C EP1 Control Res7 Reserved 7 Data Sheet End Address 0000 0081 ADM8513 Data Sheet Registers Description Note Offset Address Page Number 82~ ...

Page 27

... ADM8513 Data Sheet Registers Description Page Number ...

Page 28

... ADM8513 Data Sheet Registers Description Page Number ...

Page 29

... SW can read the register SW can read the register SW can read the register, with write mask the register can be cleared (1 clears) SW can read the register, with write mask the register can be cleared (1 clears) 29 ADM8513 Data Sheet Registers Description Page Number ...

Page 30

... HW (1 pdi clock cycle) Register is readable and writable by SW. Description Offset 00 H Description Ethernet Transmission Enable Ethernet Receive Enable Receive Pause Frame Enable Wake-on-LAN Mode Enable Status Append at the End of Received Packet Enable 30 ADM8513 Data Sheet Registers Description Reset Value 09 H Rev. 1.21, 2005-12-05 ...

Page 31

... HDM, Half-duplex mode B 1 FDM, Full-duplex mode B 10mode 0 10Base, 10Base-T mode B 1 100Base, 100Base-T mode B Reset MAC After write 1, HW will clear this bit after MAC reset. MII Mode 0 MIIM, MII mode B Reserved 31 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 32

... FABP, Filters all bad packet B 1 RBPP, Receives bad packets which pass the address filter B EP3 Read Cleared 0 AEP3, Access EP3, no effect to those registers OEP3, Once EP3 is accessed, those registers (2B-2F, 7A) will be B cleared. 32 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 33

... Res18 Reserved 18 Res19 Reserved 19 Res20 Reserved 20 Res21 Reserved 21 Res22 Reserved 22 Res23 Reserved 23 Res24 Reserved 24 Res25 Reserved 25 Data Sheet Offset 03 H Description Reserved 33 ADM8513 Data Sheet Registers Description Reset Value 00 Offset Address Page Number ...

Page 34

... Multicast Address 1 Field Bits Type MAB1 7:0 rw Data Sheet Offset 08 H Description Multicast 0 Multicast address byte [7:0] Offset 09 H Description Multicast 1 Multicast address byte [15:8] 34 ADM8513 Data Sheet Registers Description Offset Address Page Number 82~FF H Reset Value 00 Reset Value 00 Rev. 1.21, 2005-12-05 H ...

Page 35

... Bits Type MAB2 7:0 rw Multicast Address 3 MA3 Multicast Address 3 Field Bits Type MAB3 7:0 rw Data Sheet Offset 0A H Description Multicast 2 Multicast address byte [23:16] Offset 0B H Description Multicast 3 Multicast address byte [31:24] 35 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 36

... Bits Type MAB4 7:0 rw Multicast Address 5 MA5 Multicast Address 5 Field Bits Type MAB5 7:0 rw Data Sheet Offset 0C H Description Multicast 4 Multicast address byte [39:32] Offset 0D H Description Multicast 5 Multicast address byte [47:40] 36 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 37

... Bits Type MAB6 7:0 rw Multicast Address 7 MA7 Multicast Address 7 Field Bits Type MAB7 7:0 rw Data Sheet Offset 0E H Description Multicast 6 Multicast address byte [55:48] Offset 0F H Description Multicast 7 Multicast address byte [63:56] 37 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 38

... Data Sheet Offset 10 H Description Ethernet ID 0 The 1st byte of Ethernet ID is automatically loaded from EEPROM after HW reset. Offset 11 H Description Ethernet ID 1 The 2nd byte of Ethernet ID. 38 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 39

... EID3 Ethernet ID 3 Field Bits Type EID3 7:0 rw Data Sheet Offset 12 H Description Ethernet ID 2 The 3rd byte of Ethernet ID. Offset 13 H Description Ethernet ID 3 The 4th byte of Ethernet ID. 39 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 40

... EID5 Ethernet ID 5 Field Bits Type EID5 7:0 rw Data Sheet Offset 14 H Description Ethernet ID 4 The 5th byte of Ethernet ID. Offset 15 H Description Ethernet ID 5 The 6th byte of Ethernet ID. 40 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 41

... This field specifies the threshold for transmitting the PAUSE frame. As the received packet number is more than or equal to this field, the PAUSE frame is sent automatically by HW. Flow Control Packet 1 RPN, Enables pause frame transmission based on received packet B number 41 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H ...

Page 42

... NAK, EP1 sends 1-byte for more than 1 plus frame_interval ms NAK, EP1 sends 1-byte for more than 3 plus frame_interval ms NAK, EP1 sends 1-byte ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 04 H Rev. 1.21, 2005-12-05 ...

Page 43

... H Description ROM Data Low EEPROM Write: The data set in this register will be written to EEPROM EEPROM Read: The data red from EEPROM will be stored in this register Offset ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Reset Value ...

Page 44

... Field Bits Type ROMDH 7:0 rw Data Sheet Description ROM Data High EEPROM Write: The data set in this register will be written to EEPROM EEPROM Read: The data read from EEPROM will be stored in this register 44 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 45

... SW sets this bit after it well setting the rom_offset. Write Access to EEPROM Set initiate a write access to EEPROM. SW set this bit after it well setting the rom_offset, romdata_lo and romdata_hi. Offset 25 H Description MII PHY Address 45 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 46

... HW set this register when read data from PHY register. Offset 27 H Description PHY Data High SW set this register when write to PHY register. HW set this register when read data from PHY register. 46 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H ...

Page 47

... USB Bus in Resume State Set indicate usb bus in resumed state. Clear by SW read this register. USB Bus in Suspend State Set indicate usb bus in suspended state. Clear by SW read this register. 47 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value ...

Page 48

... Carrier Loss Set indicate carrier loss. Clear this register by SW Read or after EP3 is accessed. Jabber Time Out Set indicate jabber time out. Clear this register by SW Read or after EP3 is accessed. 48 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 49

... Description RX Pause Set indicate a PAUSE frame is received. Clear this register by SW Read or after EP3 is accessed. RX Overflow Set indicate external SRAM overflow. Clear this register by SW Read or after EP3 is accessed. 49 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev ...

Page 50

... Clear this register by SW Read or after EP3 is accessed. Offset 2F H Description RX Lost Packet Counts The [7:0] of lost packet counts due to receive FIFO overflow. Clear this register by SW Read or after EP3 is accessed. Offset ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Reset Value 00 H ...

Page 51

... Wakeup Frame 0 Offset WUF0O_0 Wakeup Frame 0 Offset Field Bits Type F0O 7:0 rw Data Sheet Description The 128 Mask Bits for Frame 0 Offset 40 H Description Offset for Wakeup Frame 0 51 ADM8513 Data Sheet Registers Description Offset Address Page Number ...

Page 52

... Wakeup Frame 0 CRC High Field Bits Type F0CRCH 7:0 rw Data Sheet Offset 41 H Description The Low Byte of CRC16 Match for Frame 0 Offset 42 H Description The High Byte of CRC16 Match for Frame 0 52 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 53

... Wakeup Frame 1 Mask 14 WUF1M_15 Wakeup Frame 1 Mask 15 Wakeup Frame 1 Offset WUF1O Wakeup Frame 1 Offset Data Sheet Offset 48 H Description The 128 Mask Bits for Frame 1 Offset ADM8513 Data Sheet Registers Description Reset Value 00 Offset Address Page Number ...

Page 54

... Field Bits Type F1O 7:0 rw Data Sheet Description Offset for Wakeup Frame 1 54 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 55

... Wakeup Frame 1 CRC High Field Bits Type F1CRCH 7:0 rw Data Sheet Offset 59 H Description The Low Byte of CRC16 Match for Frame 1 Offset 5A H Description The High Byte of CRC16 Match for Frame 1 55 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 56

... Wakeup Frame 2 Mask 14 WUF2M_15 Wakeup Frame 2 Mask 15 Wakeup Frame 2 Offset WUF2O Wakeup Frame 2 Offset Data Sheet Offset 60 H Description The 128 Mask Bits for Frame 2 Offset ADM8513 Data Sheet Registers Description Reset Value 00 Offset Address Page Number ...

Page 57

... Field Bits Type F2O 7:0 rw Data Sheet Description Offset for Wakeup Frame 2 57 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 58

... Wakeup Frame 2 CRC High Field Bits Type F2CRCH 7:0 rw Data Sheet Offset 71 H Description The Low Byte of CRC16 Match for Frame 2 Offset 72 H Description The High Byte of CRC16 Match for Frame 2 58 ADM8513 Data Sheet Registers Description Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 59

... Enable Wakeup Frame 2 Set enable wakeup frame2 wakeup function 1 EWF2, Enables wakeup frame2 wakeup function B CRC-16 Initial Type 0 CRC16, CRC-16 initial contents = 0000 B 1 CRC16, CRC-16 initial contents = ffff B 59 ADM8513 Data Sheet Registers Description Reset Value Rev. 1.21, 2005-12-05 ...

Page 60

... RMP, Means ADM8513/X receives a magic packet B Receives a Link Status Change Set by HW when link status change.Clear by SW read this register. 1 RLS, Means ADM8513/X receives a link status change B Receives a Wakeup Frame Set by HW when receive a wakeup frame.Clear by SW read this register. 1 RWF, Means ADM8513/X receives a wakeup frame ...

Page 61

... OUT, GPIO4 is used for output B GPIO4 Output Value When GPIO4 is used for output, this value is driven to GPIO4 pin. GPIO4 Input Value When GPIO4 is used for input, this field reflects the status of GPIO4. Default is pulled-down. 61 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 62

... GPIO0 Output Value When GPIO0 is used for output, this value is driven to GPIO0 pin. Set by SW. GPIO0 Input Value When GPIO0 is used for input, this field reflects the status of GPIO0. Set by HW. 62 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 63

... GPIO2 Output Value When GPIO2 is used for output, this value is driven to GPIO2 pin. Set by SW. GPIO2 Input Value When GPIO2 is used for input, this field reflects the status of GPIO2. Set by HW. 63 ADM8513 Data Sheet Registers Description Reset Value 00 H Rev. 1.21, 2005-12-05 ...

Page 64

... PHY Identifier 1 PHYI2 PHY Identifier 2 ANA Auto-Negotiation Advertisement Data Sheet Offset 80 H Description Reserved Offset 81 H Description Reserved End Address 0000 0006 ADM8513 Data Sheet Registers Description Reset Value 00 Reset Value 00 Note Offset Address Page Number ...

Page 65

... SW can read and write this register Register is readable and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. 65 ADM8513 Data Sheet Registers Description Page Number 72 72 Rev. 1.21, 2005-12-05 ...

Page 66

... Table 74 Registers Clock DomainsRegisters Clock Domains Clock Short Name 6.2.1 PHY Registers Data Sheet Description 66 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 67

... NO, Normal operation B 1 PD, Power Down B Isolate 0 NO, normal operation B 1 IPHY, isolate PHY from MII B Restart Autonegotiation 1 RAN, Restart Auto-neg B Duplex Mode 0 HA, Half B 1 FU, Full B Collision Test Not implemented 67 ADM8513 Data Sheet Registers Description Reset Value 1000 H Rev. 1.21, 2005-12-05 ...

Page 68

... PHY is not 100BASE-X half duplex capable B 1 100HD, PHY is 100BASE-X half duplex capable B 10 Mbit/s Full Duplex 0 10FDN, PHY is not 10 Mbit/s Full duplex capable B 1 10FD, PHY is 10 Mbit/s Full duplex capable B 68 ADM8513 Data Sheet Registers Description Reset Value 7849 H Rev. 1.21, 2005-12-05 ...

Page 69

... ANN, PHY cannot auto-negotiate B 1 AN, PHY can auto-negotiate B Link Status 0 LD, Link is down B 1 LU, Link Jabber Detect 1 JCD, Jabber condition detected B Extended Capability 0 BSC, Basic register set capabilities only B 1 EC, Extended register capabilities B 69 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 70

... PHY Identifier[31-16] OUI (bits 3-18) Offset 3 H Description PHY Identifier[15-10] OUI (bits 19-24) PHY Identifier[9-4] Manufacturer’s Model Number (bits 5-0) PHY Identifier[3-0] Revision Number (bits 3-0);Register 3, bit bit of PHY Identifier 70 ADM8513 Data Sheet Registers Description Reset Value 001D H Reset Value 2411 H Rev. 1.21, 2005-12-05 ...

Page 71

... Half Duplex Technology ability bit A0 0 10NHD, Unit is not capable of Half Duplex 10BASE 10HD, Unit is capable of Half Duplex 10BASE-T B Selector Field Identifies type of message being sent. Currently only one value is defined. 71 ADM8513 Data Sheet Registers Description Reset Value 0001 H Rev. 1.21, 2005-12-05 ...

Page 72

... Technology Ability Link Partner technology ability field. Selector Field Link Partner selector field Offset 6 H Description Parallel Detection Fault 0 NFD, No fault detected B 1 FD, Local Device Parallel Detection Fault B 72 ADM8513 Data Sheet Registers Description Reset Value 0000 H Reset Value 0004 H Rev. 1.21, 2005-12-05 ...

Page 73

... Page Received 0 NPR, A New Page has not been received B 1 PR, A New Page has been received B Link Partner Auto Negotiation Able 0 NAN, Link Partner is not Auto negotiation able B 1 AN, Link Partner is Auto negotiation able B 73 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...

Page 74

... Suspend Mode 142 mA @ 10M Full Duplex Mode 152 mA @ 100M Full Duplex Mode °C 150 – 125 W – 2000 V – Unit Note / Test Condition Max. 3.6 V – 150 mA – Unit Note / Test Condition Max. – V – 0.8 V – – V – Rev. 1.21, 2005-12-05 ADM8513 Data Sheet ...

Page 75

... Values Min. Typ. V 1.8 – -0.5 – ± 1 – 2.4 – – – – – ADM8513 Data Sheet EEPROM Interface DC Specification Unit Note / Test Condition Max. 2.5 V – 3.6 V – 0.3 V – 2.0 V – Unit Note / Test Condition Max. 5.5 V – 1.0 V – V ± 1000 nA 3 ...

Page 76

... A software reset is accomplished by setting the reset bit (bit 4) of the Ethernet Control Register (address 01 This software reset will reset all registers to default values. • When ADM8513/X sees an SE0 on USB bus for more than 2.5 s. This USB reset will reset all registers to default values 9.2 ...

Page 77

... The polling interval for endpoint 3. If this value is 0, EP3 is disabled. 0A[ select internal USB transceiver. 0A[4:2]= 000 Refer to Pin assignment The low byte of language ID. The high byte of language ID. The low byte of manufacture ID. The high byte of manufacture ID. 77 EEPROM Interface & Example t EECSH t EEDOP EEDOH Rev. 1.21, 2005-12-05 ADM8513 Data Sheet ...

Page 78

... Uses internal Ethernet PHY, Wakes on Lan en 0C-0D 0904 Language ID 0409 10-11 A607 manufacture ID 07A6 12-13 8513 product ID 8513 14 0E manufacture string length 0E bytes 15 10 manufacture string starts from word offset 10h, thus byte offset 20 Data Sheet EEPROM Interface & Example 78 Rev. 1.21, 2005-12-05 ADM8513 Data Sheet . H ...

Page 79

... UNICODE encoded string 30- 1E:descriptor size 30 bytes 03: string descriptor 20 55........: UNICODE encoded string 00................ 50- 0A: descriptor size 10 bytes 03: string descriptor 31 00 30........: UNICODE encoded string Data Sheet EEPROM Interface & Example 79 Rev. 1.21, 2005-12-05 ADM8513 Data Sheet . ...

Page 80

... Package Figure 6 Package Data Sheet 80 ADM8513 Data Sheet Package Rev. 1.21, 2005-12-05 ...

Page 81

... Make an example: Parameter “E” (9mm) means the distance between the two opposite sides. Parameter "e" (0.8mm) means the distance between two adjacent pins. D&E1 means body size. Data Sheet 81 ADM8513 Data Sheet Package Rev. 1.21, 2005-12-05 ...

Page 82

... BSC. 0.220 0.220 0.008 0.008 0.003 0.008 0.007 0.008 0.020 BSC. 0.197 0.197 0.008 0.008 0.003 0.003 0.007 0.008 Rev. 1.21, 2005-12-05 ADM8513 Package Max. 0.063 0.006 0.057 0.008 – 7° – 13° 13° 0.008 0.030 – 0.018 0.011 0.011 ...

Page 83

... Table 84 Dimensions for 48 Pin LQFP Package (cont’d) Symbol Millimeter (mm aaa bbb ccc ddd Data Sheet 0.50 BSC. 5.50 5.50 Tolerance of Form and Position 0.20 0.20 0.08 0.08 83 ADM8513 Data Sheet Package Inch 0.020 BSC. 0.217 0.217 0.008 0.008 0.003 0.003 Rev. 1.21, 2005-12-05 ...

Page 84

... If you can't avoid those designs, please add a Resistor between Crystal (or OSC) and ADM8513/X chip clk48_I pin as figure show: CLKIN To pin 29 : clk48_I Figure 7 Placement 1 • Place the filtering capacitor as closed as possible at the Vcc pin of ADM8513/X and its trace must be short and wide. Figure 8 Placement 2 Data Sheet 22.1K ...

Page 85

... Make D+ and D- traces route at the same signal plane and not pass through the other plane. – Inhibit crossover on D+ and D- – The termination resistance (R2,R3) and decoupling capacitors (C1,C2) should be closed to ADM8513/X. – D+ and D- Signal trace length should be equal and as short as possible. ...

Page 86

... Power and Ground 1 • If you use a captive cable (plus the shield wire) it may require additional filtering for EMI test pass and the length of unshielded cable should be limited to 3cm or less. Figure 13 Power and Ground 2 Data Sheet 86 ADM8513 Data Sheet Appendix Layout Guide Rev. 1.21, 2005-12-05 ...

Page 87

... Please connect 10K Ohm Ribb resistance gnd, pin40(GndRef) and pin37(GndR) first then use signal via to Gnd (Specially for 2 layers board design). Bad Figure 14 Power and Ground 3 Data Sheet Good 87 ADM8513 Data Sheet Appendix Layout Guide Rev. 1.21, 2005-12-05 ...

Page 88

Published by Infineon Technologies AG ...

Related keywords