at89c51cc03c-slsim ATMEL Corporation, at89c51cc03c-slsim Datasheet - Page 53

• Manufacturer Part Number: at89c51cc03c-slsim
• Description: At89c51cc03 Enhanced 8-bit Mcu With Can Controller And Flash Memory
• Manufacturer: ATMEL Corporation

Power Down Request
Reading the Flash Spaces
User
Extra Row
Hardware Security Byte
Flash Protection from Parallel
Programming
4182N–CAN–03/08
Before entering in Power Down (Set bit PD in PCON register) the user should check that
no write sequence is in progress (check BUSY=0), then check that the column latches
are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if
necessary.
The following procedure is used to read the User space:
•
Note:
The following procedure is used to read the Extra Row space and is summarized in
Figure 28:
•
•
•
The following procedure is used to read the Hardware
summarized in Figure 28:
•
•
Figure 28. Clear FCON to unmap the Hardware Security Byte.Reading Procedure
The three lock bits in Hardware Security Byte (see "In-System Programming" section)
are programmed according to Table 17 provide different level of protection for the on-
chip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 4
Read one byte in Accumulator by executing MOVC A,@A+DPTR with
A+DPTR=read@.
Map the Extra Row space by writing 02h in FCON register.
Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and
DPTR = FF80h to FFFFh.
Clear FCON to unmap the Extra Row.
Map the Hardware Security space by writing 04h in FCON register.
Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and
DPTR = 0000h.
FCON is supposed to be reset when not needed.
Exec: MOVC A, @A+DPTR
Flash Spaces Reading
Flash Spaces Mapping
FCON= 00000xx0b
DPTR= Address
FCON = 00h
Clear Mode
Data Read
ACC= 0
Security
space and is
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