th3122 Melexis Company, th3122 Datasheet - Page 4

• Manufacturer Part Number: th3122
• Description: K-bus Transceiver With Integrated Voltage Regulator
• Manufacturer: Melexis Company

Figure 5 - Bit Compare Pulse Diagram
SEN/STA
The pin SEN/STA is bidirectional. Used as an
output the pin indicates whether the transmit-path
is enabled or disabled:
SEN/STA =”0”
SEN/STA =”1”
Linear Regulator and Controlling Functions
Regulator
The TH3122 has an integrated linear regulator with an
output voltage of 5V ± 2 % and an output current of max.
100mA. The regulator is switched on or off with a signal
on the EN pin or wakes up with a BUS signal.
Initialization
The initialization is started if the power supply is switched
on, or after the temperature limitation has switched off
the regulator or in case of BUS traffic (wake up).
If the V
time t
Bit Compare
If the signals at the pin TxD and the pin BUS within
a specified time t
transmission will be interrupted.
If both signals at TxD and BUS are “High” within
the time t
bit-compare-function is active when the pin SEN/
STA is open (not overwritten).
3901003122
Rev 004
RES
transmission path is enabled
transmission path is disabled
CC
is started. This reset time is determined by the
voltage level is higher than V
ena
the transmission will be enabled. The
bc
are not identical, the
K-Bus Transceiver with integrated Voltage Regulator
RESEIN
, the reset
Page 4
Using this pin as an input the transmission path
can be overwritten (independent of bit-compare
and constant-low function):
SEN/STA=”0”
SEN/STA=”1”
Constant Low Switch Off
A falling edge at pin TxD (from “1” to “0”) starts the
internal constant low timer (SEN/STA open).
If the low level “0” is valid for the time t
transmission unit of the TH3122 will be disabled.
The receive unit is still active. A high level “1” at
TxD with a minimum pulse width of t
constant low timer.
Transmitting is not possible until TxD and BUS is
High for the time t
Figure 6 - Constant Low Pulse Diagram
voltage level on the VTR pin (see table VTR
Programming). After t
output is generated (see figure 7 - Initialization).
The regulator is active and can only be switched off with
a falling edge on EN. The regulator remains with
EN=high in active mode and therefore the V
also active.
SEN/STA
TxD
forcing the transmission path free
disable the transmission path
ena
.
RES
a rising edge on the RESET
t
low
t < t
rec
TH3122
rec
CC
resets the
t
ena
voltage is
low
Dec/04
the