cp2120 Silicon Laboratories, cp2120 Datasheet - Page 14

• Manufacturer Part Number: cp2120
• Description: Single Chip Spi To I2c Transfer Integrated Clock; No External Clock Required On-chip Voltage Monitor
• Manufacturer: Silicon Laboratories

CP2120
The transaction time-out counter, which terminates an I
configured through the I2CTO Internal Register. If the time-out counter is not enabled, the CP2120 will make only
one attempt at executing an I
The SPI Master can assign an I
address is not necessary for device operation. If set, the CP2120 will ACK this address when another I
on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding
as an I
14
Internal Register Address:
Internal Register Address:
Internal Register Address: 0x02
2
Internal Register Definition 1. I2CCLOCK: I
C slave.
I2CCK7
I2CAD7
TO6
R/W
Bit 7
R/W
Bit 7
R/W
Bit 7
Reset Value:
Reset Value:
Reset Value:
Bit 7-Bit 0:
Bit 7-1:
Bit 7-0:
I2CCK6
I2CAD6
Bit 0:
TO5
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
Internal Register Definition 3. I2CADR: I
Internal Register Definition 2. I2CTO: I
2
C transaction and abort if that transaction attempt fails.
TO6-0: Time Out Value
I2CAD7-0: I
Sets I2C bus address.
0xA0
I2CCK7-0: I
maximum register value = 255)
0x03
0x00
TEN:Time Out Enable Bit.
0: Disable Timer.
1: Enable Timer.
0x05
0x00
2
C address to the CP2120 by writing to the I2CADR Internal Register. Setting this
I2CCK5
I2CAD5
TO4
Bit 5
Bit 5
Bit 5
R/W
R/W
R/W
Equation 2. CTO Time-Out Frequency
2
2
Time-out Frequency
C Address
C Clock Frequency Configuration value (minimum register value = 5,
I2CCK4
I2CAD4
TO3
R/W
Bit 4
R/W
Bit 4
R/W
Bit 4
Rev. 0.3
2
C transaction after a set period of time has passed, can be
I2CCK3
I2CAD3
TO2
R/W
R/W
R/W
Bit3
Bit3
Bit3
=
2
C Clock Frequency Configuration
--------- - Hz
128
TO
(
)
I2CCK2
I2CAD2
TO1
2
Bit 2
Bit 2
Bit 2
R/W
R/W
R/W
C Time Out
2
C Address
I2CCK1
I2CAD1
TO0
R/W
Bit 1
R/W
Bit 1
R/W
Bit 1
I2CCK0
I2CAD0
TEN
R/W
Bit 0
R/W
Bit 0
R/W
Bit 0
2
C Master