jlc1563 ON Semiconductor, jlc1563 Datasheet
jlc1563
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jlc1563 Summary of contents
Page 1
... Currently, systems complexity and I2C–bus device types and functionality are only increasing result of I2C–bus loading the Clock line and Data line signals degrade. The JLC1563 I2C–Bus Transceiver restores clean signals in the system leading to improvements in system performance and reliability. ...
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... SCL 1 SCL 2 SDA 1 SDA 2 Reset 1 Reset 2 SCL to Master Comp Reset 1 Power–on Reset 2 Comp Bus Controller SDA to Master JLC1563 PIN CONNECTIONS CASE 626/968 Reset SCL Reset 2 SDA SCL 2 GND 4 5 SDA 2 PIN LIST MASTER Serial Clock ...
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... Tri–State Leakage Current Output = High Impedance; V out = GND Offset Voltage (Reset 1, Reset 2) Input Pin Capacitance Output Pin Capacitance In/Out Pin Capacitance Quiescent Supply Current (per package) JLC1563 Symbol V DD –0 –0 0.5 V out –0 0.5 ...
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... OTHER UNITS SLAVE DEVICES BUS TRANSCEIVER SIGNALS <<WRITE MODE>> SCL from Master S SDA from Master SDA from Slave from Master to Slave from Slave to Master JLC1563 APPLICATION BLOCK SCL BUS TRANSCEIVER SDA1 SDA2 SCL1 SCL2 BUS TRANSCEIVER SDA1 SDA2 SCL1 ...
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... Master BUS TRANSCEIVER SIGNALS (during RESET) <<WRITE MODE>> SCL from Master S SDA from Master SDA from Slave Reset from Master ON to Slave OFF from Slave to Master JLC1563 BUS TRANSCEIVER SIGNALS Address ...
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... BUS TRANSCEIVER SIGNALS (during RESET) <<READ MODE>> SCL from Master S SDA from Master SDA from Slave Reset from Master to Slave from Slave to Master BUS CONDITION KEY START SA = SLAVE ACKNOWLEDGE MA = MASTER ACKNOWLEDGE P = STOP JLC1563 Address DATA (I) OFF ...
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... SCL Clock HI Hold Time SDA Data Hold Time SDA Data Setup Time SDA and SCL Signal Rise Time SDA and SCL Signal Fall Time STOP Condition Setup Time SDA t LOW t BUF SCL t HD:STA JLC1563 Guaranteed Limits Symbol Min BUF 4.7 t HD:STA 4.0 t LOW 4 ...
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... Maximum Output Rise Time SDA Maximum Group Delay tPHL:SCL–tPHL:SDA Maximum Group Delay tPLZ:SCL–tPLZ:SDA Power On Reset Pulse Width TIMING CONDITIONS ( 5.0 V) Parameter Minimum Pulse Width Reset JLC1563 Guaranteed Limits Nominal Nominal 25 C Symbol Min t PHL:SCL – – t PLZ:SCL – – ...
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... PHL:SCL , t PLZ:SCL , t PHL:SDA , t PLZ:SDA , t THL:SCL , t THL:SDA 90% Input 50% SCL1 / SDA1 Output SCL2 / SDA2 (2) t PHL:SCL–SDA , t PLZ:SCL–SDA Input SCL1 DATA = L Output SDA1, SDA2 DATA = H (3) t PLZ:RES Input Reset1 / Reset2 Output SDA1, SDA2 http://onsemi.com JLC1563 10% t PHL 90% 50% 10% 10% t THL t F 90% 50% 10% ...
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... JLC1563 (4) t W:POR , t W:RES W:POR POR (INTERNAL) Reset 1,2 TEST CIRCUIT SCL2 50 pf SDA2 50 pf http://onsemi.com t > < 1 W:POR t W:RES 2 ...
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... NOTE 2 C –T– N SEATING PLANE 0.13 (0.005 JLC1563 SOEIAJ–8 M SUFFIX CASE 968–01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI L E Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSION D AND E DO NOT INCLUDE MOLD Q 1 FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE ...
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... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 JLC1563/D ...