at42qt113b ATMEL Corporation, at42qt113b Datasheet - Page 13

• Manufacturer Part Number: at42qt113b
• Manufacturer: ATMEL Corporation

4.2
4.3
9525B–AT42–09/10
Option Strapping
Power Supply, PCB Layout
The option pins OPT1 and OPT2 should never be left floating. If they are floated, the device will
draw excess power and the options will not be properly read on power-up. Intentionally, there
are no pull-up resistors on these lines, since pull-up resistors add to power drain if tied low.
The Gain input should be connected to either Vdd or Gnd.
Table 3-1 on page 9
See
than 600 µA in most cases, but can be higher if Cs is large. Increasing Cx values will actually
decrease power drain. Operation can be from batteries, but be cautious about loads causing
supply droop (see
As battery voltage sags with use or fluctuates slowly with temperature, the QT113B will track
and compensate for these changes automatically with only minor changes in sensitivity.
If the power supply is shared with another electronic system, care should be taken to assure that
the supply is free of digital spikes, sags, and surges which can adversely affect the QT113B.
The QT113B will track slow changes in Vdd, but it can be affected by rapid voltage steps.
if desired, the supply can be regulated using a conventional low current regulator, for example
CMOS regulators that have low quiescent currents. Bear in mind that such regulators generally
have very poor transient line and load stability; in some cases, shunting Vdd to Vss with a 4.7 k
resistor to induce a continuous current drain can have a very positive effect on regulator
performance.
Parts placement: The chip should be placed to minimize the SNS2 trace length to reduce low
frequency pickup, and to reduce stray Cx which degrades gain. The Cs and Rseries resistors
(see
the SNS2 trace between Rseries and the SNS2 pin is very short, thereby reducing the
antenna-like ability of this trace to pick up high frequency signals and feed them directly into the
chip.
For best EMC performance the circuit should be made entirely with SMT components.
SNS trace routing: Keep the SNS2 electrode trace (and the electrode itself) away from other
signal, power, and ground traces including over or next to ground planes. Adjacent switching
signals can induce noise onto the sensing signal; any adjacent trace or ground plane next to or
under either SNS trace will cause an increase in Cx load and desensitize the device.
For proper operation a 100nF (0.1 µF) ceramic bypass capacitor must be used directly between
Vdd and Vss; the bypass capacitor should be placed very close to the device’s power pins.
Section 5.2 on page 15
Figure 1-1 on page
Section 3.2.5 on page
and
3) should be placed as close to the body of the chip as possible so that
Table 3-2 on page 10
for the power supply range. At 3 volts current drain averages less
12).
show the option strap configurations available.
AT42QT113B
13