u6264a ETC-unknow, u6264a Datasheet

no-image

u6264a

Manufacturer Part Number
u6264a
Description
Standard Sram
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
u6264aDC
Manufacturer:
ZMD
Quantity:
4 130
Part Number:
u6264aDC
Manufacturer:
ZMD
Quantity:
4 130
Part Number:
u6264aDC
Manufacturer:
ZMD
Quantity:
20 000
Part Number:
u6264aDC-07
Manufacturer:
ZMD
Quantity:
20 000
Part Number:
u6264aDC-07LL
Manufacturer:
ZMD
Quantity:
5 530
Part Number:
u6264aDC-07LL
Manufacturer:
ZMD
Quantity:
5 120
Part Number:
u6264aDC-07LL
Manufacturer:
ZMD
Quantity:
1 980
Part Number:
u6264aDC-07LL
Manufacturer:
ZMD
Quantity:
20 000
Part Number:
u6264aS1A
Manufacturer:
ZMD
Quantity:
20 000
Part Number:
u6264aS1C
Manufacturer:
ZMD
Quantity:
20 000
December 12, 1997
Features
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Pin Configuration
8192 x 8 bit static CMOS RAM
70 and 100 ns Access Times
Common data inputs and
outputs
Three-state outputs
Typ. operating supply current
Data retention current
at 3 V: < 10
Standby current standard < 30 A
Standby current low power
(L) < 10 A
Standby current very low power
(LL) < 1 A
Standby current for LL-version
at 25 C and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
DQ1
DQ2
DQ0
VSS
A12
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
100 ns: 37 mA
-25 to 85 C
-40 to 85 C
70 ns: 45 mA
0 to 70 C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
PDIP
A (standard)
SOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ3
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
F
F
F
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
- Standby
- Data Retention
1
SOP28 (300 mil)
SOP28 (330 mil)
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at I
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 A typ.
Standard 8K x 8 SRAM
O
= 0 mA) drops to the
U6264A

Related parts for u6264a

u6264a Summary of contents

Page 1

... STD 883C M3015.7) F Latch-up immunity > 100 mA F Packages: PDIP28 (600 mil) SOP28 (300 mil) SOP28 (330 mil) Description The U6264A is a static RAM manu- factured using a CMOS process technology with the following ope- rating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell ...

Page 2

... U6264A Block Diagram A11 A12 A10 E2 E1 Truth Table Operating Mode E1 * Standby/not selected H Internal Read L Read L Write Characteristics All voltages are referenced (ground). SS All characteristics are valid in the power supply voltage range and in the operating temperature range specified. ...

Page 3

... V CC( 5.5 V CC( CC(DR) CC(DR CC(DR 0 U6264A Min. Max. Unit 4.5 5.5 V 2.0 V -0.3 0 Min. Max. Unit 0 ...

Page 4

... U6264A Electrical Characteristics Output High Voltage Output Low Voltage Input Leakage Current Standard & Low Power (L) High Low Very Low Power (LL) High Low Output High Current Output Low Current Output Leakage Current Standard & Low Power (L) High at Three-State Outputs Low at Three-State Outputs ...

Page 5

... HZWE dis( HZOE dis(G) Data Retention Mode E2-Controlled V CC 4 rec min min t rec cR 5 U6264A Min. Max 100 100 - 70 100 - 100 ...

Page 6

... the capacitance is 5 pF. dis(G) Conditions Symbol MHz U6264A D G Access Time 100 960 510 Min. Max. Unit Internal Code Power Consumption = Standard ...

Page 7

... AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAA 7 U6264A AAAA AAA AAAA AAA Output Data AAAA AAA Valid AAAA AAA t dis(E) t dis(E) t dis(G) AAAA AAAA AAAA AAAA AAAA ...

Page 8

... U6264A Write Cycle 2 (E1-controlled AAAA AAAA AAAA AAAA AAAA AAAA E2 AAAA AAAA AAAA AAAA AAAA AAAA W AAAA AAAA AAAA AAAA DQ i Input DQ i Output G Write Cycle 3 (E2-controlled AAAA AAAA AAAA AAAA AAAA AAAA E1 AAAA AAAA E2 AAAA AAAA AAAA AAAA ...

Page 9

... Memory Products 1998 Standard SRAM U6264A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur ...

Related keywords