ncn6804 ON Semiconductor, ncn6804 Datasheet
ncn6804
Available stocks
Related parts for ncn6804
ncn6804 Summary of contents
Page 1
... Dual Smart Card Interface IC with SPI Programming Interface The NCN6804 is a dual interface IC with serial control dedicated for Smart Card/Secure Access Module (SAM) reader/writer applications. It allows the management of two external ISO/EMV cards (Class C). An SPI bus is used to control and configure the dual interface ...
Page 2
... NCN6804 22 mH VBAT 10mF L1A VDD 0.1mF VDD INT CS CLK_SPI MISO MOSI CLK_IN I/O EN_RPU VDD GNDD Figure 1. Typical Interface Application http://onsemi.com L2A L1B L2B GND SMART CARD A S1 DET CRD_DETA GND 10mF 1 VCC CRD_VCCA 2 RST CRD_RSTA 3 CRD_CLKA CLK 4 CRD_C4A ...
Page 3
... VDD LOGIC CONTROL CLOCK 26 CLK_IN I/O MUX I EN_RPU 31 Exposed Pad GNDD 33 GND NCN6804 INT#A DET#A DET#B INT#B VDD DET#A DET#B MUX Figure 2. NCN6804 Block Diagram http://onsemi.com VDDPA INT#A 11 L1A 9 L2A 8 CRD_VCCA 10 GNDPA CRD_I/OA 6 CRD_RSTA CLK DIV 7 CRD_CLKA ...
Page 4
... STATUS bit (MISO bit b0). The device does not take any further action; particularly the DC/DC converter is neither stopped nor re-programmed by the NCN6804 the external mC to handle the situation. However, when CRD_VCC is overloaded, the NCN6804 shuts off the DC/DC converter, runs a Power Down ISO7816 sequence and reports the fault in the STATUS register (MISO register bit b0) ...
Page 5
... MISO O Master In Slave Out: SPI Data Output from the NCN6804. This STATUS byte carries the state of the interface, the serial transfer being achieved according to the programmed mode (Table 2), using the same CLK_SPI signal and during the same MOSI time frame. An external 4.7 kW pull down resistor might be necessary to avoid misunderstanding of the pin 29 voltage during the High Z state ...
Page 6
... Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur and V sup DDPA/B DDPA DDPB NCN6804 Symbol ) V DDPA/B (Note CRD_VCC V ...
Page 7
... Ceramic X7R, SMD type capacitors are mandatory to achieve the CRD_VCC ripple specifications. The ceramic capacitor has to be chosen according to its ESR (very low ESR) and DC bias features. The capacitance value can strongly vary with the DC voltage applied (see Figure 22). NCN6804 Rating ) (Note 5) DDPA ...
Page 8
... Functional operation of the device exceeding these conditions are not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Since (Typical) pullup resistor is provided by the NCN6804, the external MPU can use an Open Drain connection. On the other hand NMOS smart cards can be used straightforward. ...
Page 9
... Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. NCN6804 (-40°C to +85°C temperature range unless otherwise noted) + 0.30V ...
Page 10
... PROGRAMMING Write Register " WRT_REG (Is Low Only) Similar to the NCN6001, the NCN6804's WRT_REG register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as depicted in Tables 1 and 2. These bits are concatenated into 1 byte [MSB0,LSB0] in order to accelerate the programming sequence. The register can be updated when CS is low only. ...
Page 11
... Select NCN6804 device # 1 Asynchronous Card B (Note 8) b7 010 Select NCN6804 device # 2 Asynchronous Card A (Note 8) 011 Select NCN6804 device # 2 Asynchronous Card B (Note 8) 100 NA 101 Set Card Detection Switch polarity, Set SPI_MODE normal or special , Set CRD_CLKA & B slopes Fast or Slow 110 Select External Synchronous Card A ...
Page 12
... MOSI command Card A or Card B Selection - Multiplexed Mode The bit b5 in the MOSI sequence enables the selection of the NCN6804's interface (see Table 2) to the exception of the addresses {100} decoded with no effect on the device and {101} used to program device general configuration ...
Page 13
... Asynchronous Mode In this mode, the S1 pin is used to define the physical address (by comparison with the bit b6 (MOSI)) of the interfaces when a bank NCN6804 (total of 4 interfaces) shares the same digital bus. Synchronous Mode In this mode, the CLK_IN clock input and the I/O input/output are not used ...
Page 14
... CRD_C8 CRD_RST Figure 3. Startup CRD_VCC Sequence Figure 4. Measured Typical Startup CRD_VCC Sequence NCN6804 At powerup, the CRD_VCCA/B turn-on time depends upon the current capability of the DC/DC converter associated with the external inductor L and the reservoir capacitor connected across CRD_VCCA or B and GROUND. During this sequence, the average input current is 300 mA typical (see Figure 4), assuming the system is fully loaded during the start up ...
Page 15
... Figure 6. Figure 7: Start Up Sequence with ATR. Powerdown Sequence The NCN6804 provides an automatic Power Down sequence, according to the ISO7816-3 specifications. When a power down sequence is enabled the communication session terminates immediately. The sequence is launched under a micro-controller decision, when the card is extracted, or when the CRD_VCCA/B voltage is overloaded ...
Page 16
... Table 6. Table 6. I/O PULLUP RESISTOR TABLE EN_RPU I/O Pullup Resistor Low Open Disconnected High Internal 18 kW Pullup Active NOTE typical value NCN6804 V CC 200 CARD ENABLE LOGIC AND POR LEVEL SHIFT SEQ 1 Figure 8. Basic I/O Internal Circuit Figure 9. Typical I/O rise & ...
Page 17
... For each case the MISO status obtained will be compared with the MISO state prior to the interrupt. When 2 NCN6804 devices share the same digital SPI bus the software to poll the devices using again the MISO register to identify the reason of the interrupt ...
Page 18
... The product communicates to the external micro controller by means of a serial link using a Synchronous Port Interface protocol, the CLK_SPI being Low or High during the idle state. The NCN6804 is not intended to operate as a Master controller, but executes commands coming from the MPU. The CLK_SPI, CS and MOSI signals are under the microcontroller's responsibility ...
Page 19
... When 2 SPI dual bytes are sequentially transferred on the MOSI line, the CLK_SPI sequence must be separated by at least one half positive period of this clock (see td parameter). The oscillograms given Figures 14 and 15 illustrate the SPI communication protocol. Special mode NCN6804 Select Chip from SYNCHRONOUS Bank Chip Nx tdclk ...
Page 20
... At this point, Cycle 1 is completed and Cycle 2 takes place. The ON time is a function of the battery voltage and the value of the inductor network (L NCN6804 Figure 16). The operation is fully automatic and, beside the output voltage programming, does not need any further adjustment. ...
Page 21
... Figure 19. Typical Inductor Current According to the ISO7816-3 and EMV specifications recommended the interface limits the CRD_VCC output current to 200 mA maximum, under short circuit conditions. The NCN6804 supports such a parameter, the limit being depending upon the input and output voltages as depicted Figure 20. http://onsemi.com ...
Page 22
... Card operating frequency from the external clock source. 3. Controls the clock state according to the smart card specification. In addition, the NCN6804 adjusts the signal coming from the mC to get the Duty Cycle window as defined by the ISO7816-3 specification. The byte content of the SPI port b2 and b3 fulfills the programming functions when CS is Low as depicted Figures 22 and 23 ...
Page 23
... NCN6804 In order to avoid any duty cycle out of the smart card ISO7816-3 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio (see Figure 22). Consequently, the output CRD_CLKA/B frequency division can be Internal delayed by four CLOCK_IN pulses and the micro controller ...
Page 24
... Figure 25. Example of PCB Device Implementation NCN6804 Battery Voltage: Both the Over and Undervoltage are detected by the NCN6804, the READ_REG register being updated accordingly. The external MPU can read the register through the MISO pin to take whatever is appropriate to cope with the situation. ...
Page 25
... REF b 0.180 0.250 0.300 D 5.00 BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 --- --- L 0.300 0.400 0.500 SOLDERING FOOTPRINT* 5.30 3.20 3. 0.50 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCN6804/D ...