zxcw6100 Diodes, Inc., zxcw6100 Datasheet
zxcw6100
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zxcw6100 Summary of contents
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... Use of Technology” 24 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER SUMMARY The ZXCW6100S28 is part of the Acoustar™ range of new generation digital audio power devices from Zetex. It has a level of performance not offered by any other solution and with minimal components forms a complete audio interface from digital audio data to the loudspeaker ...
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... ZXCW6100S28 DESCRIPTION The ZXCW6100 is part of a new generation of stereo digital audio power amplifier devices. The device offers a move forward to a new level of performance not offered by another solution. The ZXCW6100 operates in direct drive mode and can be selected to be with or without dead time. ...
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... All clocks & data static Conditions OUT OH(min OUT OUT(max Conditions OUT OH(min OUT OUT(max ZXCW6100S28 Min Typ Max Unit 3 3.3 3 Min Typ Max Unit 10.5 A 112 144 mA 380 475 mW Min Typ Max Unit ...
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... ZXCW6100S28 DIGITAL INPUT WITH ACTIVE PULL-DOWN CHARACTERISTICS Symbol Parameter V High level input voltage IH V Low level input voltage IL I Low level Input current IL I High level Input current IH I Input capacitance C DIGITAL OUTPUT CHARACTERISTICS Symbol Parameter V High level output voltage OH V Low level output voltage ...
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... SPI-DA Data hold time spidh t time to valid SPI-DA data out spidov t SPI-EN hold time spies t SPI-EN hold time spieh t SPI-EN minimum high time spiemh 1 Note: M-CK = Master Clock Cycles. ISSUE 2 - FEBRUARY 2004 ZXCW6100S28 Conditions Min 0.5 0.1 0.7 0.1 3 Conditions Min 0.5 0.1 Load capacitance ( 50pf L 0.7 0 Typ ...
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... ZXCW6100S28 SWITCHING CHARACTERISTICS: AUDIO INPUT DATA Symbol Parameter B BIT-CK clock frequency CK t S-DATA set-up time sds t S-DATA hold time sph t WORD-CLK set-up time wcks t WORD-CLK hold time wckh 1 Note: M-CK = Master Clock Cycles. MASTER CLOCK TO PWM OUTPUT CHARACTERISTICS Symbol Parameter t M-CK to PWM output delay ...
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... TYPICAL CHARACTERISTICS 15 10 100Hz Boost 5 200Hz Boost 0 200Hz Cut -5 100Hz Cut -10 -15 10k 20k 10 7 ZXCW6100S28 12kHz Boost 8kHz Boost Flat 4kHz Boost Response 4kHz Cut 8kHz Cut 12kHz Cut 100 1k 10k 20k Frequency (Hz) Treble Response ...
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... ZXCW6100S28 PINOUT DIAGRAM PIN DESCRIPTIONS Pin Name Type 1 SPI-EN LVTTL IP 2 SPI-DA LVTTL I/O 3 SPI-CK LVTTL IP 4 CSLO LVTTL IP+PU Connect to logic Gnd 5 CSL1 LVTTL IP+PU Connect to logic Gnd 6 VCC-LOGIC 7 GND-LOGIC 8 WORD-CK LVTTL IP 9 BIT-CK LVTTL IP 10 S-DATA LVTTL IP 11 MUTE LVTTL IP+PU Mute enable, active low ...
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... BLOCK DIAGRAM FUNCTIONAL DEVICE DESCRIPTION The ZXCW6100 device is an integrated stereo digital amplifier. It takes in digital audio data, in any of the common digital audio formats, processes it and delivers a PWM direct drive left and right channel output. The direct drive PWM output can be used to ...
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... Master clock Essential to the performance of the system is the provision of a low jitter clock to the ZXCW6100 device, a jitter of less than +/-1ns is required. As well as low jitter the master clock needs consistent mark to space ratio. This master clock is generated from the external audio system, consistency needs to be better than 3ns with a 33MHz master clock ...
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... The recommended mode of operation for new users is HPWM. Chip select It is possible to cascade several ZXCW6100 devices for multi-channel applications. Each chip is accessed using the appropriate SPI enable line. Valid data for the individual ZXCW6100 is clocked in during SPI enable low periods. SPI data and clock can be common. A separate enable line per device is required ...
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... In read mode (figure 2) the host controller sends the first 8 preamble control bits with the R/W bit set high. The SPI-DA pin of the ZXCW6100 device changes state from being an input to being an output on the falling edge following the R/W bit. The device then reads out the data from the internal SPI register onto the SPI-DA wire ...
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... The audio input utilises three pins, WORD-CK, BIT-CK and S-DATA. The diagrams below indicate the appropriate timing diagrams for the 4 possible input formats. Left Justify 24 bit 2 24 bit I S Compatible Right Justify bit ISSUE 2 - FEBRUARY 2004 ZXCW6100S28 ...
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... Mode (dead/no dead time) MODE0 and MODE1 are used to set the operating mode of the ZXCW6100 device. There are two modes available, direct drive with and without dead time. Without dead time the output stage on and off switching to the N and P channel MOSFETs occurs at the same time ...
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... ISSUE 2 - FEBRUARY 2004 ZXCW6100S28 Comments/Example vl8.............vl0 011111110 is 0dB 100110000 is +25 dB 001000001 is -94.5dB 001000000 = soft mute 011111010 is default power up See volume code tables vr8.............vr0 011111110 is 0dB 100110000 is +25 dB 001000001 is -94.5dB 001000000 = soft mute ...
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... ZXCW6100S28 SPI bi-directional interface register (cont) Bit No. Function Bit Identifier 32 50/15 s standard de0 33 de-emphasis de1 34 novaload novl 35 novaload mode novlm 36 dc dither dcadd 37 limiter lar0 38 attack rate lar1 39 lar2 40 limiter lrr0 41 release rate lrr1 42 lrr2 43 lrr3 44 digital interface dif0 45 dif1 46 ATAPI mix ...
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... The treble corner frequency is selected by bits 30 & 31 4kHz 01 = 8kHz 10 = 12kHz 50/15 s Standard De-emphasis The ZXCW6100 incorporates a standard 50/15 s digital de-emphasis filter. De-emphasis is applicable in single speed mode only. Bits 32 and 33 match to sampling frequencies as below de-emphasis 01 = 44.1kHz 10 = 32kHz 11 = 48kHz 17 ...
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... ZXCW6100S28 DC Dither A function is provided to help eliminate small signal digital zero point switching distortion by the addition of a small DC voltage. This is intended to move the signal away from the DAC zero to prevent the distortion that is sometimes discernible when the DAC switches around zero. DC Dither would be required when using the recommended HPWM mode ...
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... Bit 63 RPWM The resultant operating modes are shown in the following table: hspd hpwm Operating mode 0 0 RPWM at 500kHz 1 0 RPWM at 1MHz HPWM 1 Note: recommended mode of operation ISSUE 2 - FEBRUARY 2004 1 = high speed 1 = HPWM 19 ZXCW6100S28 ...
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... ZXCW6100S28 TYPICAL CONNECTION DIAGRAM The following shows a typical connection diagram for the output circuit of one channel of the ZXCW6100 device. For dedicated Applications Notes please contact your nearest Zetex office. TYPICAL PERFORMANCE CHARACTERISTICS Parameter Conditions THD+N HPWM 1W Dynamic range Noise floor ...
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... ISSUE 2 - FEBRUARY 2004 ZXCW6100S28 ...
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... ZXCW6100S28 ISSUE 2 - FEBRUARY 2004 22 ...
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... ISSUE 2 - FEBRUARY 2004 ZXCW6100S28 ...
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... ZXCW6100S28 PACKAGE OUTLINE ORDERING INFORMATION DEVICE PART MARKING ZXCW6100S28 Zetex Acoustar™ ZXCW6100 © Zetex plc 2002 Europe Zetex plc Zetex GmbH Fields New Road Streitfeldstraße 19 Chadderton D-81673 München Oldham, OL9 8NP United Kingdom Germany Telephone (44) 161 622 4422 Telefon: (49 ...