74lcx74sjx-nl Fairchild Semiconductor, 74lcx74sjx-nl Datasheet

74lcx74sjx-nl

Manufacturer Part Number

74lcx74sjx-nl

Description

74lcx74 Low Voltage Dual D-type Positiveedge-triggered Flip-flop With 5v Tolerant Inputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LCX74SJX-NL.pdf (11 pages)

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74LCX74M

74LCX74MX_NL

(Note 2)

74LCX74SJ

74LCX74BQX

(Note 1)

74LCX74MTC

74LCX74MTCX_NL

(Note 2)

74LCX74

Low Voltage Dual D-Type Positive

Edge-Triggered Flip-Flop with 5V Tolerant Inputs

General Description

The LCX74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

the outputs until the next rising edge of the Clock Pulse

input.

Asynchronous Inputs:

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: DQFN package available in Tape and Reel only.

Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Order Number

LOW input to S

LOW input to C

Clear and Set are independent of clock

Simultaneous LOW on C

Q HIGH

(Set) sets Q to HIGH level

(Clear) sets Q to LOW level

MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

Package

Number

MTC14

M14D

M14A

and S

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MO-241, 2.5 x 3.0mm

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

makes both Q and

DS012414

Features

5V tolerant inputs

2.3V–3.6V V

7.0 ns t

Power down high impedance inputs and outputs

Implements patented noise/EMI reduction circuitry

Latch-up performance exceeds JEDEC 78 conditions

ESD performance:

Leadless Pb-Free DQFN package

24 mA output drive (V

Package Description

Human body model

Machine model

max (V

specifications provided

200V

3.3V), 10

2000V

3.0V)

March 1995

Revised February 2005

A I

www.fairchildsemi.com

max

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