74abt823d NXP Semiconductors, 74abt823d Datasheet

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74abt823d

Manufacturer Part Number
74abt823d
Description
9-bit D-type Flip-flop With Reset And Enable 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
3. Quick reference data
The 74ABT823 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data and address paths
of buses carrying parity.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master
reset input (MR) which are ideal for parity bus interfacing in systems using many
microprocessors.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
Table 1:
GND = 0 V; T
Symbol Parameter
t
t
C
C
I
PLH
PHL
CC
I
O
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 02 — 7 February 2005
High-speed parallel registers with positive edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and 32 mA
Latch-up protection:
ESD protection:
Power-on 3-state
Power-on reset
JESD78: exceeds 500 mA
MIL STD 883 method 3015: exceeds 2000 V
Machine model: exceeds 200 V
propagation delay CP to Qn C
propagation delay CP to Qn C
input capacitance
output capacitance
quiescent supply current
Quick reference data
amb
= 25 C.
Conditions
V
outputs disabled;
V
outputs 3-state;
V
V
I
O
CC
I
L
L
= 0 V or V
= GND or V
= 50 pF; V
= 50 pF; V
= 0 V or V
= 5.5 V;
CC
CC
CC
CC
CC
= 5 V
= 5 V
Product data sheet
Min
-
-
-
-
-
Typ
4.3
4.4
4
7
0.5
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
A

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74abt823d Summary of contents

Page 1

D-type flip-flop with reset and enable; 3-state Rev. 02 — 7 February 2005 1. General description The 74ABT823 bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width ...

Page 2

... Ordering information Type number Package Temperature range Name 74ABT823N +85 C 74ABT823D +85 C 74ABT823DB +85 C 74ABT823PW + Functional diagram Fig 1. Logic symbol 9397 750 14551 Product data sheet 9-bit D-type flip-flop with reset and enable; 3-state ...

Page 3

Philips Semiconductors Fig 3. Logic diagram 9397 750 14551 Product data sheet 9-bit D-type flip-flop with reset and enable; 3-state FF0 FF1 ...

Page 4

Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 3: Symbol GND 9397 750 ...

Page 5

Philips Semiconductors Table 3: Symbol Functional description 7.1 Function table Table 4: Operating mode Clear Load and read data L Hold High-impedance [ HIGH voltage level LOW voltage level ...

Page 6

Philips Semiconductors 8. Limiting values Table 5: In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 7

Philips Semiconductors 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V input diode voltage IK V HIGH-level output voltage OH V ...

Page 8

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I 3-state output current OZ I output HIGH-state leakage CEX current I output current O I quiescent supply current ...

Page 9

Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter t set-up time LOW su( hold time HIGH h( ...

Page 10

Philips Semiconductors 12. Waveforms Fig 5. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and Fig 6. Master reset (MR) pulse width, propagation delay master reset (MR) to output (Qn) 9397 750 14551 Product data sheet ...

Page 11

Philips Semiconductors Fig 7. Set-up and hold times data output (Dn) to clock (CP) and clock enable input (CE) to Fig 8. 3-state output (Qn) enable and disable times 9397 750 14551 Product data sheet 9-bit D-type flip-flop with reset ...

Page 12

Philips Semiconductors a. Input pulse definition b. Test circuit Fig 9. Load circuitry for switching times Table 9: Input V I 3.0 V 9397 750 14551 Product data sheet 9-bit D-type flip-flop with reset and enable; 3-state ...

Page 13

Philips Semiconductors 13. Package outline DIP24: plastic dual in-line package; 24 leads (300 mil) seating plane pin 1 index 1 DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. ...

Page 14

Philips Semiconductors SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. ...

Page 15

Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

Page 16

Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 17

Philips Semiconductors 14. Revision history Table 10: Revision history Document ID Release date 74ABT823_2 20050207 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Section ...

Page 18

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 19

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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