24lc515t-i-sm Microchip Technology Inc., 24lc515t-i-sm Datasheet - Page 10

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24lc515t-i-sm

Manufacturer Part Number
24lc515t-i-sm
Description
512k I2c Cmos Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet
24AA515/24LC515/24FC515
7.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK, and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
DS21673F-page 10
Note:
ACKNOWLEDGE POLLING
Care must be taken when polling the
24LC515. The control byte that was used
to initiate the write needs to match the
control byte used for polling.
FIGURE 7-1:
Initiate Write Cycle
Send Control Byte
Write Command
with R/W = 0
Condition to
Acknowledge
Send Stop
Send Start
Did Device
(ACK = 0)?
Operation
Send
Next
ACKNOWLEDGE
POLLING FLOW
© 2005 Microchip Technology Inc.
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