at49lh004 ATMEL Corporation, at49lh004 Datasheet - Page 16

• Manufacturer Part Number: at49lh004
• Description: 4-megabit Firmware Hub And Low-pin Count Flash Memory
• Manufacturer: ATMEL Corporation

8. Response to Invalid FWH/LPC Fields
8.1
8.1.1
8.1.2
8.1.3
8.2
8.2.1
16
FWH Cycles
LPC Cycles
AT49LH004
ID Mismatch
Address Out of Range
Invalid MSIZE Field
Address Out of Range
During FWH/LPC operations, the device will not explicitly indicate that it has received invalid
field sequences. The response to specific invalid fields or sequences is outlined in the follow-
ing paragraphs.
If the IDSEL field does not match ID[3:0], then the device will ignore the FWH cycle. The
device will then enter standby mode when the FWH4/LFRAME pin is brought high and no
internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-imped-
ance state.
The FWH address sequences is seven fields long (28 bits), but only the last six address fields
(A23 - A0) will be decoded. Therefore, address bits A27 - A24 will be ignored. In addition,
because of the device density, address bits A23 and A21 - A19 will be ignored. Address bit
A22 is used to determine whether reads or writes to the device will be directed to the memory
array (A22 = 1) or to the register space (A22 = 0).
If the device receives an invalid size field during a read or write operation, the internal state
machine will reset and no operation will be attempted. The device will generate no response of
any kind in this situation. Invalid size fields for a read or write cycle are anything but 0000b. In
addition, when accessing register space, invalid field sizes are anything but 0000b.
Once valid START, IDSEL, and MSIZE fields are received, the device will always respond to
subsequent inputs as if they were valid. As long as the states of FWH/LAD[3:0] and
FWH4/LFRAME are known, the response of the device to signals received during the FWH
cycle should be predictable. The device will make no attempt to check the validity of incoming
Flash operation commands.
The LPC address sequences is eight fields long (32 bits), but only the last six address fields
(A23 - A0) will be decoded. Therefore, address bits A31 - A24 will be ignored. Address bits
A22 - A19 will be decoded based on the strapping values on the ID[3:0] pins. Address bit A23
is used to determine whether reads or writes to the device will be directed to the memory array
(A23 = 1) or to the register space (A23 = 0).
Once valid START and CYCTYPE + DIR fields are received, the device will always respond to
subsequent inputs as if they were valid. As long as the states of FWH/LAD[3:0] and
FWH4/LFRAME are known, the response of the device to signals received during the LPC
cycle should be predictable. The device will make no attempt to check the validity of incoming
Flash operation commands.
3383D–FLASH–6/05