w942516bh ETC-unknow, w942516bh Datasheet
w942516bh
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w942516bh Summary of contents
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... Power Down Mode ................................................................................................................................. 23 Mode Register Operation........................................................................................................................ 23 17. TIMING WAVEFORMS....................................................................................................................27 Command Input Timing .......................................................................................................................... 27 Timing of the CLK Signals ...................................................................................................................... 27 Read Timing (Burst Length = 4).............................................................................................................. 28 Write Timing (Burst Length = 4).............................................................................................................. 29 DM, DATA MASK (W942508BH /W942504BH) ..................................................................................... BANKS Publication Release Date: March 19, 2002 - 1 - W942516BH 16 BIT DDR SDRAM Revision A1 ...
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... DM, DATA MASK (W942516BH)............................................................................................................ 30 Mode Register Set (MRS) Timing........................................................................................................... 31 Extend Mode Register Set (EMRS) Timing ............................................................................................ 32 Auto Precharge Timing (Read cycle ......................................................................................... 33 Auto Precharge Timing (Write Cycle) ..................................................................................................... 35 Read Interrupted by Read ( 8).................................................................................... 36 Burst Read Stop ( ....................................................................................................................... 36 Read Interrupted by Write & BST ( ............................................................................................. 37 Read Interrupted by Precharge ( ...
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... W942516BH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words m process technology, W942516BH delivers a data bandwidth 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516BH is sorted into three speed grades: -7, -75 and The -7 is compliant to the 143 MHz/CL2 ...
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... W942516BH DQ15 DQ14 62 DQ13 DQ12 59 DQ11 DQ10 56 DQ9 DQ8 53 NC1 ...
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... Ground Ground for logic circuit inside DDR SDRAM. Separated power from V for I/O Buffer noise. Separated ground from V Buffer noise W942516BH DESCRIPTION A12. A8. (A10 is used for Auto Precharge) ) define the command being CS , used for output buffer, to improve DD , used for output buffer, to improve ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 8912 * 512 * W942516BH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 LDQS UDQS LDM UDM COLUMN DECODER ...
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... T STG T SOLDER OUT MIN. TYP. 2.3 2 DDQ V - 0.04 VREF REF V + 0.15 REF -0.3 -0.3 0. 0.31 REF - 0 0.2 DDQ 0.2 DDQ Q +0.9V with a pulse width < W942516BH RATING UNIT -0.3 V +0.3 DDQ -0.3 3 -55 150 260 MAX. UNIT 2.5 2 DDQ DDQ V + 0.04 V REF - V + 0.3 V DDQ ...
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... Output Minimum Sink DC Current OL (DC) I Output Minimum Source DC Current OH (DC) I Output Minimum Sink DC Current OL (DC) = 25° / OUT (DC) DDQ OUT (Peak to Peak) MIN. 2.0 2.0 4.0 - < OUT DDQ Full Strength Half Strength - 8 - W942516BH = 0.2V) DELTA MAX. (MAX.) 3.0 0.5 3.0 0.25 5.0 0.5 1.5 - MIN. MAX. UNITS - +0. ...
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... ACT ACT ACT AP AP Bank 1 Bank 1 Bank 0 Bank 0 Bank 2 Bank 2 Row e Row e Row d Col d Row f Row RANDOM READ CURRENT Timing - 9 - W942516BH MAX. UNIT -7 -75 min 110 110 110 110 2 2 for DQ ...
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... 7 2 -0.75 0.75 -0.75 0.75 0.5 0.45 0.55 0.45 0. Min. CH -0.75 0.9 1.1 0.4 0.6 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 1.25 -0.25 0.25 0.9 0.9 2.2 -0.75 0.75 -0.75 0.75 0.5 1 W942516BH -75 UNITS NOTES MIN. MAX 100000 7.5 15 -0.75 0.75 16 -0.75 0.75 0.5 0.45 0. 0.45 0.55 Min -0.75 0.9 1 0.4 0.6 0.5 nS 0.5 1.75 0.35 0. 0 ...
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... V SS SSQ. may not exceed 2% V REF(DC). = 2.3V and V = 1.19V. DDQ TT = 2.3V and V = 1.11V. DDQ system supply for signal termination resistors, is expected to be set TT . REF Publication Release Date: March 19, 2002 - 11 - W942516BH VALUE UNIT V +0.31 IH REF V -0.31 IL REF 0 DDQ 0 DDQ 1.0 V (AC) ...
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... These timing are measured at stable clock. AC DQSCK and V .Transition (rise and fall) of input signals have a fixed IH min(AC) IL max(AC) contains more than one decimal place, the result is rounded 7 5.625 nS is rounded up to 5.6 nS ICK ICK V V ISO(min) ISO(max W942516BH ICK ID(AC) ...
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... CKE signal is input level one clock cycle before the commands are issued. n-1 4. These are state designated by the BS0, BS1 signals. 5. LDM, UDM (W942516BH) 6. Power Down Mode can not entry in the burst cycle. (4) CKEN-1 CKEN DM ...
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... BST BS, CA, A10 READ/READA L BS, CA, A10 WRIT/WRITA BS, RA ACT L BS, A10 PRE/PREA X AREF/SELF L Op-Code MRS/EMRS - 14 - W942516BH ACTION Nop Nop ILLEGAL ILLEGAL Row activating Nop Refresh or Self refresh Mode register accessing Nop Nop Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ...
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... L BS, CA, A10 WRIT/WRITA H BS, RA ACT L BS, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS Publication Release Date: March 19, 2002 - 15 - W942516BH NOTES ACTION Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL 3 ILLEGAL 3 ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ...
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... BST X READ/WRIT X ACT/PRE/PREA X AREF/SELF/MRS/EMRS X DSL X NOP L X BST X READ/WRIT X ACT/PRE/PREA/ARE F/SELF/MRS/EMRS W942516BH NOTES ACTION Nop->Row active after t WR Nop->Row active after t WR ILLEGAL ILLEGAL 3 ILLEGAL 3 ILLEGAL 3 ILLEGAL 3 ILLEGAL ILLEGAL Nop->Enter precharge after t WR Nop->Enter precharge after t ...
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... Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table - 17 - W942516BH ACTION XSNR XSNR IS Publication Release Date: March 19, 2002 Revision A1 NOTES ...
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... POWER APPLIED POWER ON SREF MRS/EMRS AREF IDLE PDEX ACT PDEX PD ROW ACTIVE Write Read Read A Write A Read A PRE PRE PRE PRE CHARGE PRE - 18 - W942516BH SELF REFRESH SREFX AUTO REFRESH PD POWER DOWN BST Read Read Read Read A Read A Automatic Sequence Command Sequence ...
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... Don’t care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 4. Write Command ( RAS = "H", CAS = "L" "L", BS0, BS1 = Bank, A10 = "L" A9, A11 = Column Address) W942516BH . DDQ and ...
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... Refer to the table for specific codes. 9. Extended Mode Register Set Command ( RAS = "L", CAS = "L" "L", BS0 = "H", BS1 = "L" A12 = Register data (BL/ W942516BH ...
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... CS = "H" or CKE = "H", RAS = "H", CAS = "H") This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after t (t for Read Command) from the end of this command. XSNR XSRD W942516BH Publication Release Date: March 19, 2002 - 21 - Revision A1 ...
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... Bank Activate command, the data is read out sequentially, from the bank activate command. The input data is latched RCD . Therefore, each bank must be precharged RAS (max W942516BH ...
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... Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a . RFC Publication Release Date: March 19, 2002 - 23 - W942516BH to prevent writing WR Revision A1 ...
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... A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words Burst Length Reserved words words words Reserved A3 Addressing Mode 0 Sequential 0 Interleave - 24 - W942516BH ...
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... A0) not carried from words (address bit A0, A1) Not carried from words (address bits A2, A1 and A0) Not carried from ACCESS ADDRESS Publication Release Date: March 19, 2002 - 25 - W942516BH BURST LENGTH 2 words 4 words 8 words Revision A1 ...
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... CAS Latency Reserved Reserved Reserved Reserved Reserved 2 Reserved BS1 BS0 A12- Regular MRS Cycle 0 1 Extended MRS Cycle 1 x Reserved A0 DLL 0 Enable 1 Disable A1 Output Driver 0 Full Strength 1 Half Strength - 26 - W942516BH ...
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... CLK CLK Refer to the Command Truth Table Publication Release Date: March 19, 2002 - 27 - W942516BH IH(AC) V IL(AC Revision A1 ...
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... CK t DQSCK t DQSCK t RPRE Preamble t t DQSQ QH QA0 QA1 DA0 DA1 DQSCK t RPRE Preamble t DQSQ QA0 DA0 W942516BH t DQSCK t RPST Hi Postamble t t DQSQ DQSQ Hi-Z QA2 QA3 DA2 DA3 DQSCK t DQSCK t RPST Hi Postamble ...
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... DSSK DSSK DSSK DSSK DSH DSS DSH DSS DQSH DQSL DQSH WPST Postamble DA0 DA1 DA2 DA3 DA0 DA1 DA2 DA3 t DQSS DSH - 29 - W942516BH Publication Release Date: March 19, 2002 Revision A1 ...
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... Timing Waveforms, continued DM, DATA MASK (W942508BH /W942504BH) CLK /CLK CMD WRIT DQS DM DQ DM, DATA MASK (W942516BH) CLK /CLK CMD WRIT LDQS LDM DQ0~ DQ7 UDQS UDM DQ8~ DQ15 DIPW Masked t DIPW DIPW ...
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... Reserved A11 "0" A12 "0" BS0 "0" Mode Register Set or Extended Mode Register Set "0" BS1 * "Reserved" should stay "0" during MRS cycle. W942516BH t MRD NEXT CMD Burst Length Sequential Reserved ...
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... Set BS1 "0" * "Reserved" should stay "0" during EMRS cycle. t MRD NEXT CMD DLL Switch A0 Enable 0 Disable 1 Output Driver Size A1 Full Strength 0 Hall Strength 1 MRS or EMRS BS1 BS0 Regular MRS cycle 0 0 Extended MRS cycle W942516BH ...
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... In this case, the internal precharge operation begin after BL/2 cycle from READA command. AP Represents the start of internal precharging. The Read with Auto precharge command cannot be interrupted by any other command. tCK t RAS READA READA READA W942516BH tRP AP ACT ACT ACT ...
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... Represents the start of internal precharging. The Read with Auto Precharge command cannot be interrupted by any other command. tRAS (min) – (BL/2) tCK t RAS READA Q0 Q1 READA READA W942516BH t RP ACT AP AP ACT Q3 AP ACT (min) has command. RAS ...
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... DQS BL=8 WRITA CMD DQS The Write with Auto Precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging . t DAL AP t DAL W942516BH ACT ACT t DAL AP ACT Publication Release Date: March 19, 2002 Revision A1 ...
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... CAS Latency=2 DQS DQ CAS Latency=2.5 DQS DQ READ A READ RCD CCD CCD COl,Add,A Col,Add,B Col,Add,C BST CAS Latency CAS Latency W942516BH READ C READ D READ CCD CCD Col,Add,D Col,Add,E QA0 QA1 QB0 QB1 QC0 ...
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... CAS Latency=2 DQS DQ CAS Latency=2.5 DQS DQ BST WRIT BST WRIT PRE CAS Latency CAS Latency W942516BH Publication Release Date: March 19, 2002 Revision A1 ...
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... CCD CCD COl. Add. A Col.Add.B Col. Add. C DA0 DA1 DB0 READ t WTR Data masked by READ command, DQS input ignored W942516BH WRIT D WRIT CCD CCD Col. Add. D Col. Add. E DB1 DC0 DC1 DD0 DD1 ...
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... CLK CLK WRIT CMD DQS DM DQ Data masked by PRE command, DQS input ignored. READ t WTR Data must be masked by DM PRE Data must be masked W942516BH ACT Publication Release Date: March 19, 2002 Revision A1 ...
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... RP(a) t RCD(b) t RAS(b) Preamble Postamble CL(a) Q0a APa t RC(b) t RC(a) ACTb READAa READAb t RCD( RAS(a) RP(a) t RCD(b) t RAS(b) Preamble CL(a) CL(b) Q0a Q1a APa - 40 - W942516BH t RRD ACTa ACTb t RP(b) Preamble Postamble CL(b) Q1a Q0b Q1b APb t RRD ACTa ACTb t RP(b) Postamble Q2a Q3a Q0b Q1b Q2b Q3b APb ...
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... RAS(b) CL(a) t RC( RRD RRD ACTb READAa ACTc READAb RCD(a) t RAS(a) t RCD(b) t RAS(b) t RCD(c) t RAS(c) Preamble CL(a) Q0a Q1a APa - 41 - W942516BH t RRD ACTd READAb ACTa READAc RCD(c) t RAS(c) t RCD(d) t RAS(d) Preamble Postamble Preamble CL(b) Q0a Q1a Q0b Q1b APa APb t RRD ACTd READAc ...
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... Precharged Power Down Mode Entry and Exit Timing CLK CLK t IH CKE CMD NOP AREF NOP t RFC Entry Exit NOP Entry Exit NOP - 42 - W942516BH AREF CMD NOP t RFC t IS NOP CMD NOP t IS NOP CMD NOP ...
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... Self Refresh Entry and Exit Timing CLK CLK CKE CMD PREA NOP SELF t RP Entry SELF Entry XSNR t XSRD SELFX NOP ACT NOP Exit - 43 - W942516BH t IS SELFX NOP CMD Exit READ NOP Publication Release Date: March 19, 2002 Revision A1 ...
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... PACKAGE DIMENSION TSOP 66l – 400 mil - 44 - W942516BH ...
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... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 45 - W942516BH DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...