at45db041b ATMEL Corporation, at45db041b Datasheet - Page 15

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at45db041b

Manufacturer Part Number
at45db041b
Description
At45db041b 4-megabit 2.5-volt Or 2.7-volt Dataflash
Manufacturer
ATMEL Corporation
Datasheet

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ALTERA
0
11. AC Waveforms
11.1
11.2
11.3
Note:
3443D–DFLSH–2/08
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
Reset Timing (Inactive Clock Polarity Low Shown)
The CS signal should be in the high state before the RESET signal is deasserted.
RESET
SCK
SO
CS
SI
SCK
SCK
SO
SO
CS
CS
SI
SI
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
HIGH IMPEDANCE
HIGH Z
HIGH IMPEDANCE
t
CSS
t
t
SU
t
V
CSS
t
SU
t
VALID IN
WL
VALID IN
VALID OUT
t
WH
t
WH
t
t
V
HO
tH
t
H
t
WL
VALID OUT
t
HO
t
CSH
t
CSH
t RST
t REC
t
HIGH IMPEDANCE
t
HIGH IMPEDANCE
t
t
DIS
DIS
CS
CS
HIGH IMPEDANCE
AT45DB041B
t CSS
15

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