at45db021d-ssh-sl955 ATMEL Corporation, at45db021d-ssh-sl955 Datasheet
at45db021d-ssh-sl955
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at45db021d-ssh-sl955 Summary of contents
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... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB021D is a 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB021D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
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... To allow for simple in-system reprogrammability, the AT45DB021D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB021D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GND. 3. Block Diagram WP PAGE (256/264 BYTES) BUFFER (256/264 BYTES) SCK CS RESET VCC GND 3638F–DFLASH–4/08 Figure 2- GND 6 VCC 5 WP FLASH MEMORY ARRAY I/O INTERFACE SI AT45DB021D (1) UDFN Top View SCK GND 2 7 RESET VCC ...
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... Memory Array To provide optimal flexibility, the memory array of the AT45DB021D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
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... A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. 3638F–DFLASH–4/08 specification. The Continuous Array Read bypasses the data buffer and leaves the AT45DB021D . To perform a CAR1 5 ...
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... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is AT45DB021D 6 specification. The Continuous Array Read bypasses the data CAR1 ...
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... A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, 3638F–DFLASH–4/08 AT45DB021D SCK . The D1H CAR1 ...
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... CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register will indicate that the part is busy. AT45DB021D 8 . During this time, the status register will indicate that the part is busy. ...
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... SE AT45DB021D PA2/ PA1/ PA0/ A10 • • • • • • • • • X ...
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... Only those sectors that are not protected or locked down will be erased. The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Command Chip Erase Figure 7-1. AT45DB021D 10 PA5/ PA4/ PA3/ A14 A13 ...
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... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. 3638F–DFLASH–4/08 AT45DB021D 11 ...
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... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB021D 12 Byte 1 3DH Enable Sector Protection ...
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... When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB021D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
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... Sector Protection Register. Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-127) Protect Sectors 0a (Page 0-7), 0b (Page 8-127) Note: AT45DB021D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 7 when shipped from Atmel x = don’ ...
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... Command Erase Sector Protection Register Figure 9-2. 3638F–DFLASH–4/08 Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB021D PE Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 , during CFH 15 ...
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... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB021D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
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... Dummy Byte Read Sector Protection Register Opcode X X Each transition represents 8 bits AT45DB021D Byte 1 Byte 2 Byte 3 32H xxH xxH X Data Byte Data Byte ...
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... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS SI AT45DB021D 18 Byte 1 3DH Opcode Opcode Opcode Byte 1 ...
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... Each transition represents 8 bits 3638F–DFLASH–4/08 Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB021D 0 (0a, 0b) See Below 0a 0b (Page 8-127) Bit 5, 4 Bit ...
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... Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB021D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
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... SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data bytes in the selected main memory page will be compared with 3638F–DFLASH–4/08 Opcode X X Each transition represents 8 bits AT45DB021D X Data Byte Data Byte the status register can be monitored to deter- XFR ...
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... Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit then the data in the main memory page matches the AT45DB021D 22 Figure 25-1 (page 45) is recommended ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB021D, the four bits are 0101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB021D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
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... Section 26. ”Ordering Information” on page Section 13.1). , during which time the Status Register will indicate that the device is P Byte 1 3DH CS Opcode Opcode Opcode SI Byte 1 Byte 2 Byte 3 Each transition represents 8 bits AT45DB021D 47. Byte 2 Byte 3 Byte 4 2AH 80H A6H Opcode Byte 4 25 ...
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... Byte 4 – Extended Device Information String Length Byte Count Hex Value Bit 7 Bit 6 Bit 5 Bit 4 00H 9FH Opcode SO Manufacturer ID Each transition represents 8 bits AT45DB021D 26 Bit 3 Bit 2 Bit 1 Bit Density Code Bit 3 Bit 2 Bit 1 Bit Product Version Code Bit 3 ...
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... If a Group A command is in progress (not fully completed), then another command in Group should not be started. However, during the internally self-timed portion of Group B commands 1 through 4, any command in Group C can be executed. During the internally self- timed portion of Group B commands 5 through 10, only Group C commands 3 and 4 can be exe- 3638F–DFLASH–4/08 AT45DB021D 27 ...
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... Buffer to Main Memory Page Program with Built-in Erase Buffer to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program through Buffer AT45DB021D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
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... Note: 3638F–DFLASH–4/08 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB021D Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H ...
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... D7h E8h Note Don’t Care AT45DB021D 30 Address Byte Address Byte ...
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... N AT45DB021D Address Byte ...
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... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB021D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
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... MHz mA; OUT CMOS levels CMOS levels I 1 -100 µ AT45DB021D AT45DB021D -40° 85° C 2.7V to 3.6V Min Typ Max 0 0.7 0.4 - 0.2V Units µA µA ...
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... Page Erase Time (256/264 bytes Block Erase Time (2,048/2,112 bytes Sector Erase Time (32,768/33,792 bytes Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC AT45DB021D 34 Min Typ Max Units 66 MHz 66 MHz 33 MHz 6.8 ns 6.8 ns 0.1 V/ns 0 ...
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... MHz) of the RapidS serial case. 3638F–DFLASH–4/08 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST 30 pF period. These timing waveforms are valid over the full frequency range (max- WL AT45DB021D AC MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform ...
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... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB021D CSS VALID OUT VALID ...
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... Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. 3638F–DFLASH–4/ LSB BYTE-MOSI F AT45DB021D MSB BYTE- LSB 37 ...
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... SI (INPUT) MSB Don’t Care 21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB021D 38 CMD 8 bits 8 bits Page Address Bits (A17 - A8) ...
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... BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 n X BFA7-0 X···X, BFA8 Starts self-timed erase/program operation BINARY PAGE SIZE A17- DON'T CARE BITS CMD PA9-7 PA6-0, X AT45DB021D Completes writing into the buffer n+1 Last Byte XXXX 1st byte read n+1 = 2nd byte read 39 ...
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... BUFFER 23.1 Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB021D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A17-A16 A7-A0 ...
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... A X MSB MSB ADDRESS BITS A17 - MSB MSB AT45DB021D 1 Dummy Byte BFA7 DATA BYTE MSB BIT 2047/2111 OF PAGE n ...
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... OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB021D OPCODE ADDRESS BITS A17- MSB ...
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... MSB OPCODE DON'T CARE MSB AT45DB021D DATA BYTE MSB MSB ...
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... CS 0 SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB021D OPCODE DON'T CARE ...
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... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3638F–DFLASH–4/08 START provide address (82H) END AT45DB021D and data BUFFER WRITE (84H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H) ...
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... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB021D 46 START ...
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... AT45DB021D-MH-SL954 (4) AT45DB021D-MH-SL955 AT45DB021D-SSH-B AT45DB021D-SSH-T (3) AT45DB021D-SSH-SL954 (4) AT45DB021D-SSH-SL955 AT45DB021D-SH-B AT45DB021D-SH-T (3) AT45DB021D-SH-SL954 (4) AT45DB021D-SH-SL955 Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 264 bytes. The user is able to configure these parts to a 256-byte page size if desired ...
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... UDFN D Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com AT45DB021D 48 SIDE VIEW A1 A 0.45 Option A 1 Pin #1 Chamfer (C 0.35) 2 SYMBOL TITLE 8MA1, 8-lead ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead ...
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... Colorado Springs, CO 80906 R 3638F–DFLASH–4/ TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT45DB021D Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A1 0.10 – ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB021D TOP VIEW ...
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... COMP Changed part number ordering code to reflect NiPdAu lead finish. - Changed AT45DB021D-MU to AT45DB021D-MH. - Changed AT45DB021D-SSU to AT45DB021D-SSH. - Changed AT45DB021D-SU to AT45DB021D-SH. Added lead finish details to Ordering Information table. Added Ordering Code Detail. Fixed the typographical error, under Status Register Read, to indicate that bit “0”. ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel ® RapidS and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Room 1219 ...