at45db021a ATMEL Corporation, at45db021a Datasheet
at45db021a
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at45db021a Summary of contents
Page 1
... The AT45DB021A is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 2,162,688 bits of memory are organized as 1024 pages of 264 bytes each. In addition to the main memory, the AT45DB021A also contains two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...
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... AT45DB021A does not require high input voltages for pro- gramming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read opera- tions. The AT45DB021A is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. The DataFlash supports two categories of read modes in relation to the SCK signal. The differences between the modes are in respect to the inactive state of the SCK signal as well as which clock cycle data will begin to be output ...
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... BRBD A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Burst Array Read is defined by AT45DB021A 4 the f specification. The Burst Array Read bypasses both BAR data buffers and leaves the contents of the buffers unchanged ...
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... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB021A, the three bits are 0, 1, and 0. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
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... SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the AT45DB021A 6 PA6 PA5 ...
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... Figure 2 on page 25 is recommended. Operation Mode Summary The modes described can be separated into two groups – modes which make use of the Flash memory array (Group A) and modes which do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2 ...
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... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB021A 8 SCK Mode Inactive Clock Polarity Low or High ...
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Table 4. Detailed Bit-level Addressing Sequence Opcode Opcode 50H 52H 53H ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB021A 0°C to 70°C -40°C to 85°C 2.7V to 3.6V ...
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DC Characteristics Symbol Parameter I Standby Current SB Active Current, Read I CC1 Operation Active Current, I CC2 Program/Erase Operation I Input Load Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH ...
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... SI Waveform 2 – Inactive Clock Polarity High and SPI Mode 3 CS tCSS SCK HIGH AT45DB021A 12 Output Test Load AC MEASUREMENT LEVEL times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3 ...
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Reset Timing (Inactive Clock Polarity Low Shown) CS SCK RESET HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. Command Sequence for Read/Write Operations (except Status Register Read) MSB ...
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... Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB021A 14 FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 I/O INTERFACE ...
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... BUFFER 1 BUFFER 1 (264 BYTES) BUFFER 1 READ Main Memory Page Read CS SI CMD PA9-7 SO Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read Each transition represents 8 bits and 8 clock cycles FLASH MEMORY ARRAY ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB021A DATA OUT ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB021A DATA OUT ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK ...
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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB021A DATA OUT ...
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... Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK 1 2 tSU ...
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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB021A DATA OUT ...
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... Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 tSU COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK tSU ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB021A 24 START provide address ...
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... Figure 2. Algorithm for Randomly Modifying Data MAIN MEMORY PAGE PROGRAM THROUGH BUFFER Notes preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations Page Address Pointer must be maintained to indicate which page rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer ...
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... Wide, Plastic Gull Wing Small Outline Package (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) AT45DB021A 26 Ordering Code AT45DB021A-JC AT45DB021A-RC AT45DB021A-TC AT45DB021A-JI AT45DB021A-RI AT45DB021A-TI Package Type Package Operation Range 32J Commercial 28R (0°C to 70°C) 28T 32J ...
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Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45˚ PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...
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... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...